Research output per year
Research output per year
Personal profile
Education/Academic qualification
Master of Science (Technology), Automation Engineering
Award Date: 9 Dec 2015
Bachelor of Science (Technology), Automation Engineering
Award Date: 4 Sep 2013
Fingerprint
Dive into the research topics where Panu Sjövall is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications
Sjövall, P., Lemmetti, A., Vanne, J., Lahti, S. & Hämäläinen, T., 8 Mar 2022, In: ACM Transactions on Design Automation of Electronic Systems. 27, 4, 34 p.Research output: Contribution to journal › Article › Scientific › peer-review
Open AccessFile -
High-level Synthesis Implementation of an Accurate HEVC Interpolation Filter on an FPGA
Sjövall, P., Rasinen, M., Lemmetti, A. & Vanne, J., Oct 2021, 2021 IEEE Nordic Circuits and Systems Conference (NorCAS). IEEE, 7 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Open AccessFile21 Downloads (Pure) -
High-level synthesis implementation of transform-exempted SATD architectures for low-power video coding
Partanen, T., Lemmetti, A., Sjövall, P. & Vanne, J., 2021, 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. IEEE, 5 p. 9401399. (IEEE International Symposium on Circuits and Systems proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Open AccessFile20 Downloads (Pure) -
Are We There Yet? A Study on the State of High-level Synthesis
Lahti, S., Sjövall, P., Vanne, J. & Hämäläinen, T. D., May 2019, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 5, p. 898-911Research output: Contribution to journal › Article › Scientific › peer-review
Open AccessFile17 Citations (Scopus)56 Downloads (Pure) -
Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN Cloud
Sjövall, P., Oinonen, A., Teuho, M., Vanne, J. & Hämäläinen, T. D., Oct 2019, 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEEResearch output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Open AccessFile1 Citation (Scopus)23 Downloads (Pure)
Prizes
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Best Demonstration Award
Sjövall, Panu (Recipient), 2019
Prize: Award or honor granted for a specific work
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Signal Processing: Image Communication (Journal)
Panu Sjövall (Reviewer)
May 2021Activity: Publication peer-review and editorial work › Reviewer of Scientific Journal
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IEEE International Conference on Visual Communications and Image Processing (VCIP) (Event)
Panu Sjövall (Reviewer)
2021Activity: Publication peer-review and editorial work › Reviewer of Conference Article
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IEEE International Conference on Visual Communications and Image Processing (VCIP) (Event)
Panu Sjövall (Reviewer)
2020Activity: Publication peer-review and editorial work › Reviewer of Conference Article