A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps

Miikka Tenhunen, Kalle Spoof, Vishnu Unnikrishnan, Kari Stadius, Marko Kosunen, Jussi Ryynänen

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

1 Citation (Scopus)


This paper presents a wideband 8-way time-interleaved (TI) 9-bit successive approximation register (SAR) analog-to-digital converter (ADC) with overlapping conversion steps that improve the speed of operation. The ADC generates its clocks using a synchronous counter based circuit which reduces the SAR delay. A common-mode reference based split capacitor array digital-to-analog converter (DAC) is implemented that achieves high speed and low power consumption. Simulation results are presented for the ADC designed in a 22 nm CMOS process. The TI ADC achieves at least 7.7 ENOB at 2 GS/s and consumes a total of 19.8 mW from 0.8 V supplies, resulting in 47.6 fF/conv-step. The single ADC achieves 8.34 ENOB at 250 MS/s, consuming 1.43 mW in total and 17.7 fF/conv-step.

Original languageEnglish
Title of host publication20th IEEE International Interregional NEWCAS Conference, NEWCAS 2022 - Proceedings
Number of pages5
ISBN (Electronic)9781665401050
ISBN (Print)9781665401067
Publication statusPublished - 2022
Publication typeA4 Article in conference proceedings
EventIEEE International New Circuits and Systems Conference - Quebec City, Canada
Duration: 19 Jun 202222 Jun 2022


ConferenceIEEE International New Circuits and Systems Conference
CityQuebec City


  • high-speed ADC
  • time-interleaved ADC

Publication forum classification

  • Publication forum level 1

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Networks and Communications
  • Hardware and Architecture
  • Signal Processing
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Instrumentation


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