Abstract
This paper presents a wideband 8-way time-interleaved (TI) 9-bit successive approximation register (SAR) analog-to-digital converter (ADC) with overlapping conversion steps that improve the speed of operation. The ADC generates its clocks using a synchronous counter based circuit which reduces the SAR delay. A common-mode reference based split capacitor array digital-to-analog converter (DAC) is implemented that achieves high speed and low power consumption. Simulation results are presented for the ADC designed in a 22 nm CMOS process. The TI ADC achieves at least 7.7 ENOB at 2 GS/s and consumes a total of 19.8 mW from 0.8 V supplies, resulting in 47.6 fF/conv-step. The single ADC achieves 8.34 ENOB at 250 MS/s, consuming 1.43 mW in total and 17.7 fF/conv-step.
| Original language | English |
|---|---|
| Title of host publication | 20th IEEE International Interregional NEWCAS Conference, NEWCAS 2022 - Proceedings |
| Publisher | IEEE |
| Pages | 35-39 |
| Number of pages | 5 |
| ISBN (Electronic) | 9781665401050 |
| ISBN (Print) | 9781665401067 |
| DOIs | |
| Publication status | Published - 2022 |
| Publication type | A4 Article in conference proceedings |
| Event | IEEE International New Circuits and Systems Conference - Quebec City, Canada Duration: 19 Jun 2022 → 22 Jun 2022 |
Conference
| Conference | IEEE International New Circuits and Systems Conference |
|---|---|
| Country/Territory | Canada |
| City | Quebec City |
| Period | 19/06/22 → 22/06/22 |
Keywords
- high-speed ADC
- SAR ADC
- time-interleaved ADC
Publication forum classification
- Publication forum level 1
ASJC Scopus subject areas
- Artificial Intelligence
- Computer Networks and Communications
- Hardware and Architecture
- Signal Processing
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
- Instrumentation