A Low-Power Semi-Digital Spectrum-Balancing Adaptive Equalizer for 8Gb/s Serial Links

This paper presents a high-speed semi-digital spectrum balancing adaptive equalizer (SDSB-AEQ) integrated in a receiver (RX) for high-speed display driver ICs (DDIs). The proposed SDSB-AEQ eliminates the need for passive analog filters as compared to typical spectrum balancing adaptive equalizers (SB-AEQ) by implementing an analog–digital (hybrid) processing architecture and significantly shortens the chip area and equalizer (EQ) settling time. The SDSB-AEQ digital block is RTL-synthesized and includes comparators, an FSM, and accumulators to process spectral information from the analog domain. The proposed SDSB-AEQ was designed and fabricated in a 65 nm CMOS process with an active area of 0.0769 mm2. Measurement results show that the proposed SDSB-AEQ reduces peak-to-peak jitter from 53.133 ps to 20.836 ps compared to a non-optimized fixed baseline EQ condition, corresponding to an improvement of 0.26 UI. The proposed SDSB-AEQ consumes 9 mW within a total RX power of 33 mW, and its performance is verified by measurements.