A simplified executable model to evaluate latency and throughput of networks-on-chip

L. Ost, F. G. Moraes, L. Möller, L. Soares Indrusiak, M. Glesner, S. Määttä, J. Nurmi

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    10 Citations (Scopus)
    Translated title of the contributionA simplified executable model to evaluate latency and throughput of networks-on-chip
    Original languageEnglish
    Title of host publicationSBCCI 2008, 21st Symposium on Integrated Circuits and Systems Design, Gramado, Brazil, September 1 to 4, 2008
    Pages170-175
    DOIs
    Publication statusPublished - 2008
    Publication typeA4 Article in a conference publication

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