A VHDL model and implementation of a coarse-grain reconfigurable coprocessor for a RISC core

C. Brunelli, F. Cinelli, D. Rossi, J. Nurmi

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    13 Citations (Scopus)
    Translated title of the contributionA VHDL model and implementation of a coarse-grain reconfigurable coprocessor for a RISC core
    Original languageEnglish
    Title of host publicationProceedings of the 2nd Conference on Ph. D. Research in Microelectronics and Electronics, June 12-15, 2006, Otranto, Lecce, italy
    EditorsP. Malcovati, A. Baschirotto
    Pages229-232
    Publication statusPublished - 2006
    Publication typeA4 Article in a conference publication

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