An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks

Hesam Zolfaghari; Davide Rossi; Jari Nurmi

doi:10.1109/NORCHIP.2019.8906959

An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks

Hesam Zolfaghari, Davide Rossi, Jari Nurmi

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

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Abstract

Programmable data plane is a key enabler of Software Defined Networking. By making networking devices programmable, novel networking services and functions could be realized by means of software running on these devices. In this paper, we present a lightweight packet processor that could process the packets on the fly as they arrive. As we will see, the area of this packet processor is smaller than a packet parser employing Ternary Content Addressable Memory. As an added benefit, the designed packet processor could also reduce the traffic to the lookup tables on the chip. Moreover, its use is not limited to switches and routers. It could also be used in the Network Interface Cards and offload packet processing tasks. Despite its packet processing capabilities, packet processor instances required for sustaining aggregate throughput of 640 Gbps have area equivalent to the packet parser instances in the Reconfigurable Match Tables Architecture.

Original language	English
Title of host publication	2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
Editors	Jari Nurmi, Peeter Ellervee, Kari Halonen, Juha Röning
Publisher	IEEE
ISBN (Electronic)	978-1-7281-2769-9
ISBN (Print)	978-1-7281-2770-5
DOIs	https://doi.org/10.1109/NORCHIP.2019.8906959
Publication status	Published - 29 Oct 2019
Publication type	A4 Article in conference proceedings
Event	IEEE Nordic Circuits and Systems Conference - Duration: 1 Jan 2000 → …

Conference

Conference	IEEE Nordic Circuits and Systems Conference
Period	1/01/00 → …

Publication forum classification

Publication forum level 1

ASJC Scopus subject areas

General Engineering

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10.1109/NORCHIP.2019.8906959

An Explicitly Parallel Architecture for Packet Processing 2019
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http://urn.fi/URN:NBN:fi:tuni-202002272400

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title = "An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks",

abstract = "Programmable data plane is a key enabler of Software Defined Networking. By making networking devices programmable, novel networking services and functions could be realized by means of software running on these devices. In this paper, we present a lightweight packet processor that could process the packets on the fly as they arrive. As we will see, the area of this packet processor is smaller than a packet parser employing Ternary Content Addressable Memory. As an added benefit, the designed packet processor could also reduce the traffic to the lookup tables on the chip. Moreover, its use is not limited to switches and routers. It could also be used in the Network Interface Cards and offload packet processing tasks. Despite its packet processing capabilities, packet processor instances required for sustaining aggregate throughput of 640 Gbps have area equivalent to the packet parser instances in the Reconfigurable Match Tables Architecture.",

author = "Hesam Zolfaghari and Davide Rossi and Jari Nurmi",

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booktitle = "2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)",

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note = "IEEE Nordic Circuits and Systems Conference ; Conference date: 01-01-2000",

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Zolfaghari, H, Rossi, D & Nurmi, J 2019, An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks. in J Nurmi, P Ellervee, K Halonen & J Röning (eds), 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE, IEEE Nordic Circuits and Systems Conference, 1/01/00. https://doi.org/10.1109/NORCHIP.2019.8906959

An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks. / Zolfaghari, Hesam; Rossi, Davide; Nurmi, Jari.
2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). ed. / Jari Nurmi; Peeter Ellervee; Kari Halonen; Juha Röning. IEEE, 2019.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

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N2 - Programmable data plane is a key enabler of Software Defined Networking. By making networking devices programmable, novel networking services and functions could be realized by means of software running on these devices. In this paper, we present a lightweight packet processor that could process the packets on the fly as they arrive. As we will see, the area of this packet processor is smaller than a packet parser employing Ternary Content Addressable Memory. As an added benefit, the designed packet processor could also reduce the traffic to the lookup tables on the chip. Moreover, its use is not limited to switches and routers. It could also be used in the Network Interface Cards and offload packet processing tasks. Despite its packet processing capabilities, packet processor instances required for sustaining aggregate throughput of 640 Gbps have area equivalent to the packet parser instances in the Reconfigurable Match Tables Architecture.

AB - Programmable data plane is a key enabler of Software Defined Networking. By making networking devices programmable, novel networking services and functions could be realized by means of software running on these devices. In this paper, we present a lightweight packet processor that could process the packets on the fly as they arrive. As we will see, the area of this packet processor is smaller than a packet parser employing Ternary Content Addressable Memory. As an added benefit, the designed packet processor could also reduce the traffic to the lookup tables on the chip. Moreover, its use is not limited to switches and routers. It could also be used in the Network Interface Cards and offload packet processing tasks. Despite its packet processing capabilities, packet processor instances required for sustaining aggregate throughput of 640 Gbps have area equivalent to the packet parser instances in the Reconfigurable Match Tables Architecture.

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An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks

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