Are We There Yet? A Study on the State of High-level Synthesis

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    To increase productivity in designing digital hardware components, high-level synthesis (HLS) is seen as the next step in raising the design abstraction level. However, the quality of results (QoR) of HLS tools has tended to be behind those of manual register-transfer level (RTL) flows. In this paper, we survey the scientific literature published since 2010 about the QoR and productivity differences between the HLS and RTL design flows. Altogether, our survey spans 46 papers and 118 associated applications. Our results show that on average, the QoR of RTL flow is still better than that of the state-of-the-art HLS tools. However, the average development time with HLS tools is only a third of that of the RTL flow, and a designer obtains over four times as high productivity with HLS. Based on our findings, we also present a model case study to sum up the best practices in comparative studies between HLS and RTL. The outcome of our case study is also in line with the survey results, as using an HLS tool is seen to increase the productivity by a factor of six. In addition, to help close the QoR gap, we present a survey of literature focused on improving HLS. Our results let us conclude that HLS is currently a viable option for fast prototyping and for designs with short time to market.
    Original languageEnglish
    Pages (from-to)898-911
    JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    Issue number5
    Early online date8 May 2018
    Publication statusPublished - May 2019
    Publication typeA1 Journal article-refereed


    • high-level synthesis
    • FPGA implementation
    • productivity

    Publication forum classification

    • Publication forum level 1


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