Cascoded Power Stage With Automatic Dead Time Generation

I.M. Filanovsky; J.K. Järvenhaara; N.T. Tchamov

doi:10.1109/MWSCAS.2015.7282019

Cascoded Power Stage With Automatic Dead Time Generation

I.M. Filanovsky
, J.K. Järvenhaara
, N.T. Tchamov

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

Abstract

The paper presents a cascoded power stage with automatic dead time generation. The circuit is using the inter-transistor node voltages of the cascode configuration as feedback control signals to delay turning ON the power transistors. The circuit is designed as the output stage of a fully-integrated buck converter. The steady-state operation is described. The waveforms simulated on 45-nm CMOS process show that in steady-state operation the short-circuit path and body diode conductions are avoided while effective zero-voltage switching (ZVS) are provided both for ground and power supply line; the calculated dead times are in a good agreement with simulation results.

Original language	English
Title of host publication	IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, CO, U.S.A, Aug. 2-5, 2015
Publisher	IEEE
Number of pages	4
ISBN (Print)	978-1-4673-6557-4
DOIs	https://doi.org/10.1109/MWSCAS.2015.7282019
Publication status	Published - 2 Aug 2015
Publication type	A4 Article in conference proceedings
Event	Midwest Symposium on Circuits and Systems - Duration: 1 Jan 1900 → …

Conference

Conference	Midwest Symposium on Circuits and Systems
Period	1/01/00 → …

Keywords

DC-DC converters
Buck converter
Cascoded Stage
Dead time auto-generation
ZVS

Publication forum classification

Publication forum level 1

ASJC Scopus subject areas

General Engineering
General Energy

Access to Document

10.1109/MWSCAS.2015.7282019

Cite this

@inproceedings{ea1e5a89e38f418f8a809ed6bb5b5aa9,

title = "Cascoded Power Stage With Automatic Dead Time Generation",

abstract = "The paper presents a cascoded power stage with automatic dead time generation. The circuit is using the inter-transistor node voltages of the cascode configuration as feedback control signals to delay turning ON the power transistors. The circuit is designed as the output stage of a fully-integrated buck converter. The steady-state operation is described. The waveforms simulated on 45-nm CMOS process show that in steady-state operation the short-circuit path and body diode conductions are avoided while effective zero-voltage switching (ZVS) are provided both for ground and power supply line; the calculated dead times are in a good agreement with simulation results. ",

keywords = "DC-DC converters, Buck converter, Cascoded Stage, Dead time auto-generation, ZVS",

author = "I.M. Filanovsky and J.K. J{\"a}rvenhaara and N.T. Tchamov",

year = "2015",

month = aug,

day = "2",

doi = "10.1109/MWSCAS.2015.7282019",

language = "English",

isbn = "978-1-4673-6557-4",

booktitle = "IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, CO, U.S.A, Aug. 2-5, 2015",

publisher = "IEEE",

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note = "Midwest Symposium on Circuits and Systems ; Conference date: 01-01-1900",

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TY - GEN

T1 - Cascoded Power Stage With Automatic Dead Time Generation

AU - Filanovsky, I.M.

AU - Järvenhaara, J.K.

AU - Tchamov, N.T.

PY - 2015/8/2

Y1 - 2015/8/2

N2 - The paper presents a cascoded power stage with automatic dead time generation. The circuit is using the inter-transistor node voltages of the cascode configuration as feedback control signals to delay turning ON the power transistors. The circuit is designed as the output stage of a fully-integrated buck converter. The steady-state operation is described. The waveforms simulated on 45-nm CMOS process show that in steady-state operation the short-circuit path and body diode conductions are avoided while effective zero-voltage switching (ZVS) are provided both for ground and power supply line; the calculated dead times are in a good agreement with simulation results.

AB - The paper presents a cascoded power stage with automatic dead time generation. The circuit is using the inter-transistor node voltages of the cascode configuration as feedback control signals to delay turning ON the power transistors. The circuit is designed as the output stage of a fully-integrated buck converter. The steady-state operation is described. The waveforms simulated on 45-nm CMOS process show that in steady-state operation the short-circuit path and body diode conductions are avoided while effective zero-voltage switching (ZVS) are provided both for ground and power supply line; the calculated dead times are in a good agreement with simulation results.

KW - DC-DC converters

KW - Buck converter

KW - Cascoded Stage

KW - Dead time auto-generation

KW - ZVS

U2 - 10.1109/MWSCAS.2015.7282019

DO - 10.1109/MWSCAS.2015.7282019

M3 - Conference contribution

SN - 978-1-4673-6557-4

BT - IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, CO, U.S.A, Aug. 2-5, 2015

PB - IEEE

T2 - Midwest Symposium on Circuits and Systems

Y2 - 1 January 1900

ER -

Cascoded Power Stage With Automatic Dead Time Generation

Abstract

Conference

Keywords

Publication forum classification

ASJC Scopus subject areas

Access to Document

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Cite this