Challenges in integration of resonant interband tunnel devices with CMOS

Stephen Sudirgo; Branislav Curanovic; Sean L. Rommel; Karl D. Hirschman; Santosh K. Kurinec; Niu Jin; Anthony T. Rice; Paul R. Berger; Phillip E. Thompson

doi:10.1109/UGIM.2003.1225742

Challenges in integration of resonant interband tunnel devices with CMOS

Stephen Sudirgo, Branislav Curanovic, Sean L. Rommel, Karl D. Hirschman, Santosh K. Kurinec, Niu Jin, Anthony T. Rice, Paul R. Berger, Phillip E. Thompson

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

3 Citations (Scopus)

Abstract

The fabrication of SiGe Resonant Interband Tunnel Devices (RITD) using CMOS compatible processes requires ability to form RITD structures selectively on source/drain regions. Various approaches were investigated and RITDs have been realized in lithographically defined openings in oxide on Si wafers. Patterned growth RITD on p+ Si exhibited a peak-to-valley current ratio (PVCR) of 3.0 and peak current density (J_P) of 188 A/cm² whereas RITD on p+ implanted regions resulted in a PVCR of 2.5 with J_P of 278 A/cm². Blanket growth RITD on p+ implanted substrate yielded a superior PCVR of 3.3 and J_P of 332 A/cm². The observed effects of patterned growth and implanted substrate on the RITD device performance are critical challenges addressed in this study for RITD-CMOS integration.

Original language	English
Title of host publication	Proceedings of the 15th Biennial University/Government/Industry Microelectronics Symposium
Publisher	IEEE
Pages	275-278
Number of pages	4
ISBN (Print)	0-7803-7972-1
DOIs	https://doi.org/10.1109/UGIM.2003.1225742
Publication status	Published - 2003
Externally published	Yes
Publication type	A4 Article in conference proceedings
Event	15th Biennial University/Government/Industry Microelectronics Symposium - Boise, ID, United States Duration: 30 Jun 2003 → 2 Jul 2003

Publication series

Name	Biennial University/Government/Industry Microelectronics Symposium - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISSN (Print)	0749-6877

Conference

Conference	15th Biennial University/Government/Industry Microelectronics Symposium
Country/Territory	United States
City	Boise, ID
Period	30/06/03 → 2/07/03

Keywords

CMOS integration
Resonant Interband Tunneling Diodes (RITD)
Resonant Tunneling Devices

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/UGIM.2003.1225742

Cite this

Sudirgo, S., Curanovic, B., Rommel, S. L., Hirschman, K. D., Kurinec, S. K., Jin, N., Rice, A. T., Berger, P. R., & Thompson, P. E. (2003). Challenges in integration of resonant interband tunnel devices with CMOS. In Proceedings of the 15th Biennial University/Government/Industry Microelectronics Symposium (pp. 275-278). (Biennial University/Government/Industry Microelectronics Symposium - Proceedings). IEEE. https://doi.org/10.1109/UGIM.2003.1225742

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title = "Challenges in integration of resonant interband tunnel devices with CMOS",

abstract = "The fabrication of SiGe Resonant Interband Tunnel Devices (RITD) using CMOS compatible processes requires ability to form RITD structures selectively on source/drain regions. Various approaches were investigated and RITDs have been realized in lithographically defined openings in oxide on Si wafers. Patterned growth RITD on p+ Si exhibited a peak-to-valley current ratio (PVCR) of 3.0 and peak current density (JP) of 188 A/cm2 whereas RITD on p+ implanted regions resulted in a PVCR of 2.5 with JP of 278 A/cm2. Blanket growth RITD on p+ implanted substrate yielded a superior PCVR of 3.3 and JP of 332 A/cm2. The observed effects of patterned growth and implanted substrate on the RITD device performance are critical challenges addressed in this study for RITD-CMOS integration.",

keywords = "CMOS integration, Resonant Interband Tunneling Diodes (RITD), Resonant Tunneling Devices",

author = "Stephen Sudirgo and Branislav Curanovic and Rommel, {Sean L.} and Hirschman, {Karl D.} and Kurinec, {Santosh K.} and Niu Jin and Rice, {Anthony T.} and Berger, {Paul R.} and Thompson, {Phillip E.}",

year = "2003",

doi = "10.1109/UGIM.2003.1225742",

language = "English",

isbn = "0-7803-7972-1",

series = "Biennial University/Government/Industry Microelectronics Symposium - Proceedings",

publisher = "IEEE",

pages = "275--278",

booktitle = "Proceedings of the 15th Biennial University/Government/Industry Microelectronics Symposium",

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Sudirgo, S, Curanovic, B, Rommel, SL, Hirschman, KD, Kurinec, SK, Jin, N, Rice, AT, Berger, PR & Thompson, PE 2003, Challenges in integration of resonant interband tunnel devices with CMOS. in Proceedings of the 15th Biennial University/Government/Industry Microelectronics Symposium . Biennial University/Government/Industry Microelectronics Symposium - Proceedings, IEEE, pp. 275-278, 15th Biennial University/Government/Industry Microelectronics Symposium, Boise, ID, United States, 30/06/03. https://doi.org/10.1109/UGIM.2003.1225742

Challenges in integration of resonant interband tunnel devices with CMOS. / Sudirgo, Stephen; Curanovic, Branislav; Rommel, Sean L. et al.

Proceedings of the 15th Biennial University/Government/Industry Microelectronics Symposium . IEEE, 2003. p. 275-278 (Biennial University/Government/Industry Microelectronics Symposium - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

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AU - Sudirgo, Stephen

AU - Curanovic, Branislav

AU - Rommel, Sean L.

AU - Hirschman, Karl D.

AU - Kurinec, Santosh K.

AU - Jin, Niu

AU - Rice, Anthony T.

AU - Berger, Paul R.

AU - Thompson, Phillip E.

PY - 2003

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N2 - The fabrication of SiGe Resonant Interband Tunnel Devices (RITD) using CMOS compatible processes requires ability to form RITD structures selectively on source/drain regions. Various approaches were investigated and RITDs have been realized in lithographically defined openings in oxide on Si wafers. Patterned growth RITD on p+ Si exhibited a peak-to-valley current ratio (PVCR) of 3.0 and peak current density (JP) of 188 A/cm2 whereas RITD on p+ implanted regions resulted in a PVCR of 2.5 with JP of 278 A/cm2. Blanket growth RITD on p+ implanted substrate yielded a superior PCVR of 3.3 and JP of 332 A/cm2. The observed effects of patterned growth and implanted substrate on the RITD device performance are critical challenges addressed in this study for RITD-CMOS integration.

AB - The fabrication of SiGe Resonant Interband Tunnel Devices (RITD) using CMOS compatible processes requires ability to form RITD structures selectively on source/drain regions. Various approaches were investigated and RITDs have been realized in lithographically defined openings in oxide on Si wafers. Patterned growth RITD on p+ Si exhibited a peak-to-valley current ratio (PVCR) of 3.0 and peak current density (JP) of 188 A/cm2 whereas RITD on p+ implanted regions resulted in a PVCR of 2.5 with JP of 278 A/cm2. Blanket growth RITD on p+ implanted substrate yielded a superior PCVR of 3.3 and JP of 332 A/cm2. The observed effects of patterned growth and implanted substrate on the RITD device performance are critical challenges addressed in this study for RITD-CMOS integration.

KW - CMOS integration

KW - Resonant Interband Tunneling Diodes (RITD)

KW - Resonant Tunneling Devices

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Sudirgo S, Curanovic B, Rommel SL, Hirschman KD, Kurinec SK, Jin N et al. Challenges in integration of resonant interband tunnel devices with CMOS. In Proceedings of the 15th Biennial University/Government/Industry Microelectronics Symposium . IEEE. 2003. p. 275-278. (Biennial University/Government/Industry Microelectronics Symposium - Proceedings). doi: 10.1109/UGIM.2003.1225742

Challenges in integration of resonant interband tunnel devices with CMOS

Abstract

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Keywords

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