Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter

Mikko Martelius; Kari Stadius; Jerry Lemberg; Tero Nieminen; Enrico Roverato; Marko Kosunen; Jussi Ryynänen; Lauri Anttila; Mikko Valkama

doi:10.1109/ISCAS.2016.7527339

Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter

Mikko Martelius, Kari Stadius, Jerry Lemberg, Tero Nieminen, Enrico Roverato, Marko Kosunen, Jussi Ryynänen, Lauri Anttila, Mikko Valkama

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

9 Citations (Scopus)

Abstract

In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.

Original language	English
Title of host publication	ISCAS 2016 - IEEE International Symposium on Circuits and Systems
Publisher	IEEE
Pages	710-713
Number of pages	4
ISBN (Electronic)	9781479953400
DOIs	https://doi.org/10.1109/ISCAS.2016.7527339
Publication status	Published - 29 Jul 2016
Publication type	A4 Article in conference proceedings
Event	IEEE International Symposium on Circuits and Systems - Duration: 1 Jan 1900 → …

Publication series

Name
ISSN (Electronic)	2379-447X

Conference

Conference	IEEE International Symposium on Circuits and Systems
Period	1/01/00 → …

Publication forum classification

Publication forum level 1

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2016.7527339

Cite this

@inproceedings{1da3a305d86440cfa99e8beb8a16598e,

title = "Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter",

abstract = "In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.",

author = "Mikko Martelius and Kari Stadius and Jerry Lemberg and Tero Nieminen and Enrico Roverato and Marko Kosunen and Jussi Ryyn{\"a}nen and Lauri Anttila and Mikko Valkama",

year = "2016",

month = jul,

day = "29",

doi = "10.1109/ISCAS.2016.7527339",

language = "English",

publisher = "IEEE",

pages = "710--713",

booktitle = "ISCAS 2016 - IEEE International Symposium on Circuits and Systems",

note = "IEEE International Symposium on Circuits and Systems ; Conference date: 01-01-1900",

}

Martelius, M, Stadius, K, Lemberg, J, Nieminen, T, Roverato, E, Kosunen, M, Ryynänen, J, Anttila, L & Valkama, M 2016, Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter. in ISCAS 2016 - IEEE International Symposium on Circuits and Systems., 7527339, IEEE, pp. 710-713, IEEE International Symposium on Circuits and Systems, 1/01/00. https://doi.org/10.1109/ISCAS.2016.7527339

TY - GEN

T1 - Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter

AU - Martelius, Mikko

AU - Stadius, Kari

AU - Lemberg, Jerry

AU - Nieminen, Tero

AU - Roverato, Enrico

AU - Kosunen, Marko

AU - Ryynänen, Jussi

AU - Anttila, Lauri

AU - Valkama, Mikko

PY - 2016/7/29

Y1 - 2016/7/29

N2 - In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.

AB - In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.

U2 - 10.1109/ISCAS.2016.7527339

DO - 10.1109/ISCAS.2016.7527339

M3 - Conference contribution

AN - SCOPUS:84983429973

SP - 710

EP - 713

BT - ISCAS 2016 - IEEE International Symposium on Circuits and Systems

PB - IEEE

T2 - IEEE International Symposium on Circuits and Systems

Y2 - 1 January 1900

ER -

Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter

Abstract

Publication series

Conference

Publication forum classification

ASJC Scopus subject areas

Access to Document

Fingerprint

Cite this