TY - GEN
T1 - Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter
AU - Martelius, Mikko
AU - Stadius, Kari
AU - Lemberg, Jerry
AU - Nieminen, Tero
AU - Roverato, Enrico
AU - Kosunen, Marko
AU - Ryynänen, Jussi
AU - Anttila, Lauri
AU - Valkama, Mikko
PY - 2016/7/29
Y1 - 2016/7/29
N2 - In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.
AB - In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.
U2 - 10.1109/ISCAS.2016.7527339
DO - 10.1109/ISCAS.2016.7527339
M3 - Conference contribution
AN - SCOPUS:84983429973
SP - 710
EP - 713
BT - ISCAS 2016 - IEEE International Symposium on Circuits and Systems
PB - IEEE
T2 - IEEE International Symposium on Circuits and Systems
Y2 - 1 January 1900
ER -