Co-simulation of Configurable Parallel Memory Architecture and Processor

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific

Translated title of the contribution	Co-simulation of Configurable Parallel Memory Architecture and Processor
Original language	English
Title of host publication	Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, April 17-19, 2002, Brno, Czech Republic
Editors	B. Straube
Pages	310-313
Publication status	Published - 2002
Publication type	B3 Article in conference proceedings

Publication forum classification

@inproceedings{69b48cde46ca44f8a3622700b271121a,

title = "Co-simulation of Configurable Parallel Memory Architecture and Processor",

author = "J. Vanne and E. Aho and K. Kuusilinna and T. H{\"a}m{\"a}l{\"a}inen",

note = "Contribution: organisation=tkt,FACT1=1",

year = "2002",

language = "English",

pages = "310--313",

editor = "B. Straube",

booktitle = "Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, April 17-19, 2002, Brno, Czech Republic",

}

Co-simulation of Configurable Parallel Memory Architecture and Processor. / Vanne, J.; Aho, E.; Kuusilinna, K. et al.
Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, April 17-19, 2002, Brno, Czech Republic. ed. / B. Straube. 2002. p. 310-313.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific

TY - GEN

T1 - Co-simulation of Configurable Parallel Memory Architecture and Processor

AU - Vanne, J.

AU - Aho, E.

AU - Kuusilinna, K.

AU - Hämäläinen, T.

N1 - Contribution: organisation=tkt,FACT1=1

PY - 2002

Y1 - 2002

M3 - Conference contribution

SP - 310

EP - 313

BT - Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, April 17-19, 2002, Brno, Czech Republic

A2 - Straube, B.

ER -