Complexity Analysis of Next-Generation HEVC Decoder

Marko Viitanen; Jarno Vanne; Timo D. Hämäläinen; Moncef Gabbouj; Jani Lainema

doi:10.1109/ISCAS.2012.6272182

Complexity Analysis of Next-Generation HEVC Decoder

Marko Viitanen, Jarno Vanne, Timo D. Hämäläinen, Moncef Gabbouj, Jani Lainema

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

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Abstract

This paper analyzes the complexity of the HEVC video decoder being developed by the JCT-VC community. The HEVC reference decoder HM 3.1 is profiled with Intel VTune on Intel Core 2 Duo processor. The analysis covers both Low Complexity (LC) and High Efficiency (HE) settings for resolutions varying from WQVGA (416 × 240 pixels) up to 1600p (2560 × 1600 pixels). The yielded cycle-accurate results are compared with the respective results of H.264/AVC Baseline Profile (BP) and High Profile (HiP) reference decoders. HEVC offers significant improvement in compression efficiency over H.264/AVC: the average BD-rate saving of LC is around 51% over BP whereas the BD-rate gain of HE is around 45% over HiP. However, the average decoding complexities of LC and HE increase by 61% and 87% over BP and HiP, respectively. In LC, the most complex functions are motion compensation (MC) and loop filtering (LF) that account on average for 50% and 14% of the decoder complexity. The decoding complexity of HE configuration is on average 42% higher than that of the LC configuration. Majority of the difference is caused by extra LF stages. In HE, the complexities of MC and LF are 37% and 32%, respectively. In practice, a standard 3 GHz dual core processor is expected to be able to decode 1080p HEVC content in real-time.

Translated title of the contribution	Complexity Analysis of Next-Generation HEVC Decoder
Original language	English
Title of host publication	ISCAS 2012, IEEE International Symposium on Circuits and Systems, May 20-23, 2012, Seoul, Korea
Place of Publication	Piscataway, NJ
Pages	882-885
DOIs	https://doi.org/10.1109/ISCAS.2012.6272182
Publication status	Published - 2012
Publication type	A4 Article in conference proceedings
Event	IEEE International Symposium on Circuits and Systems - Duration: 1 Jan 1900 → …

Publication series

Name	IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310
ISSN (Electronic)	2158-1525

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Conference	IEEE International Symposium on Circuits and Systems
Period	1/01/00 → …

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10.1109/ISCAS.2012.6272182

Complexity Analysis of Next-Generation HEVC Decoder 2012
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title = "Complexity Analysis of Next-Generation HEVC Decoder",

abstract = "This paper analyzes the complexity of the HEVC video decoder being developed by the JCT-VC community. The HEVC reference decoder HM 3.1 is profiled with Intel VTune on Intel Core 2 Duo processor. The analysis covers both Low Complexity (LC) and High Efficiency (HE) settings for resolutions varying from WQVGA (416 × 240 pixels) up to 1600p (2560 × 1600 pixels). The yielded cycle-accurate results are compared with the respective results of H.264/AVC Baseline Profile (BP) and High Profile (HiP) reference decoders. HEVC offers significant improvement in compression efficiency over H.264/AVC: the average BD-rate saving of LC is around 51% over BP whereas the BD-rate gain of HE is around 45% over HiP. However, the average decoding complexities of LC and HE increase by 61% and 87% over BP and HiP, respectively. In LC, the most complex functions are motion compensation (MC) and loop filtering (LF) that account on average for 50% and 14% of the decoder complexity. The decoding complexity of HE configuration is on average 42% higher than that of the LC configuration. Majority of the difference is caused by extra LF stages. In HE, the complexities of MC and LF are 37% and 32%, respectively. In practice, a standard 3 GHz dual core processor is expected to be able to decode 1080p HEVC content in real-time.",

author = "Marko Viitanen and Jarno Vanne and H{\"a}m{\"a}l{\"a}inen, {Timo D.} and Moncef Gabbouj and Jani Lainema",

note = "Contribution: organisation=tkt,FACT1=0.5<br/>Contribution: organisation=sgn,FACT2=0.5<br/>Publisher name: Institute of Electrical and Electronics Engineers IEEE; IEEE International Symposium on Circuits and Systems ; Conference date: 01-01-1900",

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doi = "10.1109/ISCAS.2012.6272182",

language = "English",

isbn = "978-1-4673-0218-0",

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Viitanen, M , Vanne, J , Hämäläinen, TD , Gabbouj, M & Lainema, J 2012, Complexity Analysis of Next-Generation HEVC Decoder. in ISCAS 2012, IEEE International Symposium on Circuits and Systems, May 20-23, 2012, Seoul, Korea. IEEE International Symposium on Circuits and Systems, Piscataway, NJ, pp. 882-885, IEEE International Symposium on Circuits and Systems, 1/01/00. https://doi.org/10.1109/ISCAS.2012.6272182

Complexity Analysis of Next-Generation HEVC Decoder. / Viitanen, Marko ; Vanne, Jarno ; Hämäläinen, Timo D. et al.
ISCAS 2012, IEEE International Symposium on Circuits and Systems, May 20-23, 2012, Seoul, Korea. Piscataway, NJ, 2012. p. 882-885 (IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

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AU - Gabbouj, Moncef

AU - Lainema, Jani

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AB - This paper analyzes the complexity of the HEVC video decoder being developed by the JCT-VC community. The HEVC reference decoder HM 3.1 is profiled with Intel VTune on Intel Core 2 Duo processor. The analysis covers both Low Complexity (LC) and High Efficiency (HE) settings for resolutions varying from WQVGA (416 × 240 pixels) up to 1600p (2560 × 1600 pixels). The yielded cycle-accurate results are compared with the respective results of H.264/AVC Baseline Profile (BP) and High Profile (HiP) reference decoders. HEVC offers significant improvement in compression efficiency over H.264/AVC: the average BD-rate saving of LC is around 51% over BP whereas the BD-rate gain of HE is around 45% over HiP. However, the average decoding complexities of LC and HE increase by 61% and 87% over BP and HiP, respectively. In LC, the most complex functions are motion compensation (MC) and loop filtering (LF) that account on average for 50% and 14% of the decoder complexity. The decoding complexity of HE configuration is on average 42% higher than that of the LC configuration. Majority of the difference is caused by extra LF stages. In HE, the complexities of MC and LF are 37% and 32%, respectively. In practice, a standard 3 GHz dual core processor is expected to be able to decode 1080p HEVC content in real-time.

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DO - 10.1109/ISCAS.2012.6272182

M3 - Conference contribution

SN - 978-1-4673-0218-0

T3 - IEEE International Symposium on Circuits and Systems

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EP - 885

BT - ISCAS 2012, IEEE International Symposium on Circuits and Systems, May 20-23, 2012, Seoul, Korea

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T2 - IEEE International Symposium on Circuits and Systems

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ER -

Complexity Analysis of Next-Generation HEVC Decoder

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