Configurable Address Computation in a Parallel Memory Architecture

E. Aho, J. Vanne, K. Kuusilinna, T. Hämäläinen, J. Saarinen

    Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

    Translated title of the contributionConfigurable Address Computation in a Parallel Memory Architecture
    Original languageEnglish
    Title of host publicationAdvances in Signal Processing and Computer Technologies. Electrical and Computer Engineering Series. A Series of Reference Books and Textbooks.
    EditorsG. Antoniou
    Place of PublicationKreikka
    PublisherWSES Press
    Pages390-395
    Publication statusPublished - 2001
    Publication typeA3 Book chapter

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