Configurable Paralell Memory Implementation For Systenm-on-Chip Designs

J. Vanne, E. Aho, K. Kuusilinna, T. Hämäläinen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific

Translated title of the contribution	Configurable Paralell Memory Implementation For Systenm-on-Chip Designs
Original language	English
Title of host publication	WSOC Proceedings of the International Workshop on System on Chip for Real-time Applications, July 5 - 7, 2002, Banff, Canada
Pages	253-264
Publication status	Published - 2002
Publication type	B3 Article in conference proceedings

Publication forum classification

@inproceedings{7b3cf79474ff493184ac90472b9684a8,

title = "Configurable Paralell Memory Implementation For Systenm-on-Chip Designs",

author = "J. Vanne and E. Aho and K. Kuusilinna and T. H{\"a}m{\"a}l{\"a}inen",

note = "CD-ROM<br/>Contribution: organisation=tkt,FACT1=1",

year = "2002",

language = "English",

pages = "253--264",

booktitle = "WSOC Proceedings of the International Workshop on System on Chip for Real-time Applications, July 5 - 7, 2002, Banff, Canada",

}

TY - GEN

T1 - Configurable Paralell Memory Implementation For Systenm-on-Chip Designs

AU - Vanne, J.

AU - Aho, E.

AU - Kuusilinna, K.

AU - Hämäläinen, T.

N1 - CD-ROM<br/>Contribution: organisation=tkt,FACT1=1

PY - 2002

Y1 - 2002

M3 - Conference contribution

SP - 253

EP - 264

BT - WSOC Proceedings of the International Workshop on System on Chip for Real-time Applications, July 5 - 7, 2002, Banff, Canada

ER -