Customized High Performance Low Power Processor for Binaural Speaker Localization

N. Behmann; C. C. Seifert; G.  Paya-Vaya; H. Blume; P. Jääskeläinen; J. Multanen; H. Kultala; J. Takala; J. Thiemann; S. van de Par

doi:10.1109/ICECS.2016.7841215

Customized High Performance Low Power Processor for Binaural Speaker Localization

N. Behmann, C. C. Seifert, G. Paya-Vaya, H. Blume, P. Jääskeläinen, J. Multanen, H. Kultala, J. Takala, J. Thiemann, S. van de Par

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Abstract

This paper proposes a customized C programmable processor design to implement the propabilistic binaural speaker localization algorithm that fulfills the challenging requirements placed by the usage context. When compared to a VLIW-based processor design with similar basic computational resources and no special instructions, the proposed processor reaches a 151× speed-up. For a 28nm standard CMOS technology, power consumption of 12 mW (at 50 MHz) and silicon area of 0.3 mm2 is estimated. This is the first publication of a realistic programmable processing architecture for the probabilistic binaural speaker localization or a comparably complex algorithm for hearing aid devices.

Original language	English
Title of host publication	2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Publisher	IEEE
ISBN (Electronic)	978-1-5090-6113-6
DOIs	https://doi.org/10.1109/ICECS.2016.7841215
Publication status	Published - 2016
Publication type	A4 Article in conference proceedings
Event	IEEE International Conference on Electronics, Circuits and Systems - Duration: 31 Dec 1899 → …

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Conference	IEEE International Conference on Electronics, Circuits and Systems
Period	31/12/99 → …

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10.1109/ICECS.2016.7841215

Customized High Performance Low Power 2016
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http://urn.fi/URN:NBN:fi:tuni-202010167360

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title = "Customized High Performance Low Power Processor for Binaural Speaker Localization",

abstract = "This paper proposes a customized C programmable processor design to implement the propabilistic binaural speaker localization algorithm that fulfills the challenging requirements placed by the usage context. When compared to a VLIW-based processor design with similar basic computational resources and no special instructions, the proposed processor reaches a 151× speed-up. For a 28nm standard CMOS technology, power consumption of 12 mW (at 50 MHz) and silicon area of 0.3 mm2 is estimated. This is the first publication of a realistic programmable processing architecture for the probabilistic binaural speaker localization or a comparably complex algorithm for hearing aid devices. ",

author = "N. Behmann and {C. Seifert}, C. and G. Paya-Vaya and H. Blume and P. J{\"a}{\"a}skel{\"a}inen and J. Multanen and H. Kultala and J. Takala and J. Thiemann and {van de Par}, S.",

year = "2016",

doi = "10.1109/ICECS.2016.7841215",

language = "English",

booktitle = "2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)",

publisher = "IEEE",

note = "IEEE International Conference on Electronics, Circuits and Systems ; Conference date: 31-12-1899",

}

Behmann, N, C. Seifert, C, Paya-Vaya, G, Blume, H, Jääskeläinen, P , Multanen, J, Kultala, H, Takala, J, Thiemann, J & van de Par, S 2016, Customized High Performance Low Power Processor for Binaural Speaker Localization. in 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, IEEE International Conference on Electronics, Circuits and Systems, 31/12/99. https://doi.org/10.1109/ICECS.2016.7841215

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T1 - Customized High Performance Low Power Processor for Binaural Speaker Localization

AU - Behmann, N.

AU - C. Seifert, C.

AU - Paya-Vaya, G.

AU - Blume, H.

AU - Jääskeläinen, P.

AU - Multanen, J.

AU - Kultala, H.

AU - Takala, J.

AU - Thiemann, J.

AU - van de Par, S.

PY - 2016

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N2 - This paper proposes a customized C programmable processor design to implement the propabilistic binaural speaker localization algorithm that fulfills the challenging requirements placed by the usage context. When compared to a VLIW-based processor design with similar basic computational resources and no special instructions, the proposed processor reaches a 151× speed-up. For a 28nm standard CMOS technology, power consumption of 12 mW (at 50 MHz) and silicon area of 0.3 mm2 is estimated. This is the first publication of a realistic programmable processing architecture for the probabilistic binaural speaker localization or a comparably complex algorithm for hearing aid devices.

AB - This paper proposes a customized C programmable processor design to implement the propabilistic binaural speaker localization algorithm that fulfills the challenging requirements placed by the usage context. When compared to a VLIW-based processor design with similar basic computational resources and no special instructions, the proposed processor reaches a 151× speed-up. For a 28nm standard CMOS technology, power consumption of 12 mW (at 50 MHz) and silicon area of 0.3 mm2 is estimated. This is the first publication of a realistic programmable processing architecture for the probabilistic binaural speaker localization or a comparably complex algorithm for hearing aid devices.

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DO - 10.1109/ICECS.2016.7841215

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PB - IEEE

T2 - IEEE International Conference on Electronics, Circuits and Systems

Y2 - 31 December 1899

ER -

Customized High Performance Low Power Processor for Binaural Speaker Localization

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