Design and Analysis of Interconnection Architectures for On-Chip Digital Systems

V. Lahtinen

Research output: Book/Report › Doctoral thesis › Collection of Articles

Translated title of the contribution	Design and Analysis of Interconnection Architectures for On-Chip Digital Systems
Original language	English
Place of Publication	Tampere
Publisher	Tampere University of Technology
Publication status	Published - 2004
Publication type	G5 Doctoral dissertation (articles)

Name	Tampereen teknillinen yliopisto, Julkaisuja
Publisher	Tampere University of Technology
Volume	478
ISSN (Print)	1459-2045

Publication forum classification

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title = "Design and Analysis of Interconnection Architectures for On-Chip Digital Systems",

author = "V. Lahtinen",

note = "Awarding institution:Tampere University of Technology",

year = "2004",

language = "English",

series = "Tampereen teknillinen yliopisto, Julkaisuja",

publisher = "Tampere University of Technology",

}

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AU - Lahtinen, V.

N1 - Awarding institution:Tampere University of Technology

PY - 2004

Y1 - 2004

M3 - Doctoral thesis

T3 - Tampereen teknillinen yliopisto, Julkaisuja

BT - Design and Analysis of Interconnection Architectures for On-Chip Digital Systems

PB - Tampere University of Technology

CY - Tampere

ER -