Design and implementation of a multi-mode harris corner detector architecture

J. Li; T. Viitanen; L. Li; J. Takala; S. S. Bhattacharyya

doi:10.1109/NORCHIP.2017.8124963

Design and implementation of a multi-mode harris corner detector architecture

J. Li
, T. Viitanen
, L. Li
, J. Takala
, S. S. Bhattacharyya

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

Abstract

In this paper, we present a configurable architecture for corner detection in images based on the well-known Harris corner detection algorithm, and we demonstrate a field programmable gate array (FPGA) implementation of the proposed architecture. Our architecture is designed to be configurable across diverse operational trade-offs, which makes it useful for integration into a wide variety of application scenarios. We apply lightweight dataflow methods for design and implementation of our configurable architecture, and for experimentation with alternative combinations of transformations for design optimization across throughput, latency, and FPGA resource requirements. By using different levels of resource-sharing — in particular resource sharing within and across individual dataflow graph modules — we are able to systematically arrive at a set of efficient architectural configurations using a unified, model-based methodology.

Original language	English
Title of host publication	2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
Publisher	IEEE
Pages	1-6
Number of pages	6
ISBN (Electronic)	978-1-5386-2844-7
DOIs	https://doi.org/10.1109/NORCHIP.2017.8124963
Publication status	Published - 1 Oct 2017
Publication type	A4 Article in conference proceedings
Event	Nordic Circuits and Systems Conference and International Symposium of System-on-Chip - Duration: 1 Jan 1900 → …

Conference

Conference	Nordic Circuits and Systems Conference and International Symposium of System-on-Chip
Period	1/01/00 → …

Keywords

Algorithm design and analysis
Computer architecture
Detectors
Field programmable gate arrays
Kernel
Resource management
Smoothing methods
Computer vision
FPGA
corner detection
dataflow
model-based design

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Publication forum level 1

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10.1109/NORCHIP.2017.8124963

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@inproceedings{eefc84abaccb46fb9de41b086854526c,

title = "Design and implementation of a multi-mode harris corner detector architecture",

abstract = "In this paper, we present a configurable architecture for corner detection in images based on the well-known Harris corner detection algorithm, and we demonstrate a field programmable gate array (FPGA) implementation of the proposed architecture. Our architecture is designed to be configurable across diverse operational trade-offs, which makes it useful for integration into a wide variety of application scenarios. We apply lightweight dataflow methods for design and implementation of our configurable architecture, and for experimentation with alternative combinations of transformations for design optimization across throughput, latency, and FPGA resource requirements. By using different levels of resource-sharing — in particular resource sharing within and across individual dataflow graph modules — we are able to systematically arrive at a set of efficient architectural configurations using a unified, model-based methodology.",

keywords = "Algorithm design and analysis, Computer architecture, Detectors, Field programmable gate arrays, Kernel, Resource management, Smoothing methods, Computer vision, FPGA, corner detection, dataflow, model-based design",

author = "J. Li and T. Viitanen and L. Li and J. Takala and Bhattacharyya, \{S. S.\}",

year = "2017",

month = oct,

day = "1",

doi = "10.1109/NORCHIP.2017.8124963",

language = "English",

pages = "1--6",

booktitle = "2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)",

publisher = "IEEE",

address = "United States",

note = "Nordic Circuits and Systems Conference and International Symposium of System-on-Chip ; Conference date: 01-01-1900",

}

Li, J, Viitanen, T, Li, L, Takala, J & Bhattacharyya, SS 2017, Design and implementation of a multi-mode harris corner detector architecture. in 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE, pp. 1-6, Nordic Circuits and Systems Conference and International Symposium of System-on-Chip, 1/01/00. https://doi.org/10.1109/NORCHIP.2017.8124963

Design and implementation of a multi-mode harris corner detector architecture. / Li, J.; Viitanen, T.; Li, L. et al.
2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE, 2017. p. 1-6.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

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T1 - Design and implementation of a multi-mode harris corner detector architecture

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AU - Viitanen, T.

AU - Li, L.

AU - Takala, J.

AU - Bhattacharyya, S. S.

PY - 2017/10/1

Y1 - 2017/10/1

N2 - In this paper, we present a configurable architecture for corner detection in images based on the well-known Harris corner detection algorithm, and we demonstrate a field programmable gate array (FPGA) implementation of the proposed architecture. Our architecture is designed to be configurable across diverse operational trade-offs, which makes it useful for integration into a wide variety of application scenarios. We apply lightweight dataflow methods for design and implementation of our configurable architecture, and for experimentation with alternative combinations of transformations for design optimization across throughput, latency, and FPGA resource requirements. By using different levels of resource-sharing — in particular resource sharing within and across individual dataflow graph modules — we are able to systematically arrive at a set of efficient architectural configurations using a unified, model-based methodology.

AB - In this paper, we present a configurable architecture for corner detection in images based on the well-known Harris corner detection algorithm, and we demonstrate a field programmable gate array (FPGA) implementation of the proposed architecture. Our architecture is designed to be configurable across diverse operational trade-offs, which makes it useful for integration into a wide variety of application scenarios. We apply lightweight dataflow methods for design and implementation of our configurable architecture, and for experimentation with alternative combinations of transformations for design optimization across throughput, latency, and FPGA resource requirements. By using different levels of resource-sharing — in particular resource sharing within and across individual dataflow graph modules — we are able to systematically arrive at a set of efficient architectural configurations using a unified, model-based methodology.

KW - Algorithm design and analysis

KW - Computer architecture

KW - Detectors

KW - Field programmable gate arrays

KW - Kernel

KW - Resource management

KW - Smoothing methods

KW - Computer vision

KW - FPGA

KW - corner detection

KW - dataflow

KW - model-based design

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M3 - Conference contribution

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PB - IEEE

T2 - Nordic Circuits and Systems Conference and International Symposium of System-on-Chip

Y2 - 1 January 1900

ER -

Design and implementation of a multi-mode harris corner detector architecture

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Keywords

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