Design and Implementation of Multi-Purpose DCT/DST-Specific Accelerator on Heterogeneous Multicore Architecture

Sajjad Nouri, Ramin Ghaznavi Youvalari, Jari Nurmi

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    2 Citations (Scopus)


    This paper presents the implementation of various sizes of Discrete Cosine transform (DCT) and Discrete Sine Transform (DST) dedicated for High Efficiency Video Coding (HEVC) standard by using template-based Coarse-Grained Reconfigurable Arrays (CGRAs) as accelerators on Heterogeneous Accelerator-Rich Platform (HARP). The proposal makes multipurpose DCT/DST specific accelerators in such a way that final architecture consists of 4/8/16/32-point DCT and 4-point DST. The accelerators are primarily designed by crafting template-based CGRA devices at different dimensions and then arranging them on a Network-on-Chip platform along with a few RISC cores. In this research work, the performance of each DCT/DST-specific accelerator, the collective performance of the whole platform and the NoC traffic are recorded in terms of the number of clock cycles and several high-level performance metrics. Conducted experiments show that 4-point DCT and 4-point DST can be implemented completely in 54 and 56 clock cycles, respectively, while for 8/16/32-point DCT, 67, 179 and 354 clock cycles are required, respectively. The achieved total power dissipation and energy consumption based on post placement and routing information are equal to 4.1 W and 10.87 μJ, respectively with 256 instantiated Processing Elements (PEs) at 200.0 MHz operating frequency. It resulted to a performance of 51.2 Giga Operations Per Second (GOPS) and 12 MOPS/mW as an architectural constant for the HARP template on 28 nm Altera Stratix-V chip. The proposed architecture is able to sustain Full HD 1080p format at 30 fps on FPGA.
    Original languageEnglish
    Title of host publication2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
    ISBN (Electronic)978-1-5386-7656-1
    Publication statusPublished - 13 Dec 2018
    Publication typeA4 Article in conference proceedings
    EventIEEE Nordic Circuits and Systems Conference - Tallinn, Estonia
    Duration: 30 Oct 201831 Oct 2018


    ConferenceIEEE Nordic Circuits and Systems Conference
    Abbreviated titleNorCAS 2018

    Publication forum classification

    • Publication forum level 1

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering


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