Design and verification of a VHDL model of a floating-point unit for a RISC microprocessor

C. Brunelli, J. Nurmi

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    Translated title of the contributionDesign and verification of a VHDL model of a floating-point unit for a RISC microprocessor
    Original languageEnglish
    Title of host publicationProceedings of 2006 International Symposium on system-on-Chip, 13-16 November, 2006, Tampere, Finland
    EditorsJ. Nurmi, J. Takala
    Pages87-90
    Publication statusPublished - 2006
    Publication typeA4 Article in a conference publication

    Publication forum classification

    • No publication forum level

    Cite this