Design and verification of a VHDL model of a floating-point unit for a RISC microprocessor

C. Brunelli, J. Nurmi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

Translated title of the contribution	Design and verification of a VHDL model of a floating-point unit for a RISC microprocessor
Original language	English
Title of host publication	Proceedings of 2006 International Symposium on system-on-Chip, 13-16 November, 2006, Tampere, Finland
Editors	J. Nurmi, J. Takala
Pages	87-90
Publication status	Published - 2006
Publication type	A4 Article in conference proceedings

Publication forum classification

@inproceedings{c0b4cde112774a0dbd264b4c5b1bde61,

title = "Design and verification of a VHDL model of a floating-point unit for a RISC microprocessor",

author = "C. Brunelli and J. Nurmi",

note = "ISBN 1-4244-0621-8<br/>Contribution: organisation=tkt,FACT1=1",

year = "2006",

language = "English",

pages = "87--90",

editor = "J. Nurmi and J. Takala",

booktitle = "Proceedings of 2006 International Symposium on system-on-Chip, 13-16 November, 2006, Tampere, Finland",

}

Design and verification of a VHDL model of a floating-point unit for a RISC microprocessor. / Brunelli, C.; Nurmi, J.
Proceedings of 2006 International Symposium on system-on-Chip, 13-16 November, 2006, Tampere, Finland. ed. / J. Nurmi; J. Takala. 2006. p. 87-90.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Design and verification of a VHDL model of a floating-point unit for a RISC microprocessor

AU - Brunelli, C.

AU - Nurmi, J.

N1 - ISBN 1-4244-0621-8<br/>Contribution: organisation=tkt,FACT1=1

PY - 2006

Y1 - 2006

M3 - Conference contribution

SP - 87

EP - 90

BT - Proceedings of 2006 International Symposium on system-on-Chip, 13-16 November, 2006, Tampere, Finland

A2 - Nurmi, J.

A2 - Takala, J.

ER -