Design methodology for accelerating software executions with FPGA

Tomasz Patyk; Perttu Salmela; Teemu Pitkänen; Jarmo Takala

doi:10.1109/SIPS.2010.5624761

Design methodology for accelerating software executions with FPGA

Tomasz Patyk, Perttu Salmela, Teemu Pitkänen, Jarmo Takala

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

1 Citation (Scopus)

Translated title of the contribution	Design methodology for accelerating software executions with FPGA
Original language	English
Title of host publication	2010 IEEE Workshop on Signal Processing Systems, SiPS 2010, October 6-8, 2010, San Francisco Bay Area, California, U.S.A.
Pages	46-51
DOIs	https://doi.org/10.1109/SIPS.2010.5624761
Publication status	Published - 2010
Publication type	A4 Article in conference proceedings

Publication forum classification

No publication forum level

Access to Document

10.1109/SIPS.2010.5624761

Cite this

@inproceedings{c34c15da1af149d180073974eb4ee26b,

title = "Design methodology for accelerating software executions with FPGA",

author = "Tomasz Patyk and Perttu Salmela and Teemu Pitk{\"a}nen and Jarmo Takala",

note = "Contribution: organisation=tkt,FACT1=1",

year = "2010",

doi = "10.1109/SIPS.2010.5624761",

language = "English",

isbn = "978-1-4244-8934-3",

pages = "46--51",

booktitle = "2010 IEEE Workshop on Signal Processing Systems, SiPS 2010, October 6-8, 2010, San Francisco Bay Area, California, U.S.A.",

}

Design methodology for accelerating software executions with FPGA. / Patyk, Tomasz; Salmela, Perttu; Pitkänen, Teemu et al.
2010 IEEE Workshop on Signal Processing Systems, SiPS 2010, October 6-8, 2010, San Francisco Bay Area, California, U.S.A.. 2010. p. 46-51.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Design methodology for accelerating software executions with FPGA

AU - Patyk, Tomasz

AU - Salmela, Perttu

AU - Pitkänen, Teemu

AU - Takala, Jarmo

N1 - Contribution: organisation=tkt,FACT1=1

PY - 2010

Y1 - 2010

U2 - 10.1109/SIPS.2010.5624761

DO - 10.1109/SIPS.2010.5624761

M3 - Conference contribution

SN - 978-1-4244-8934-3

SP - 46

EP - 51

BT - 2010 IEEE Workshop on Signal Processing Systems, SiPS 2010, October 6-8, 2010, San Francisco Bay Area, California, U.S.A.

ER -