Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip

Waqar Hussain; Roberto Airoldi; Henry Hoffmann; Tapani Ahonen; Jari Nurmi

doi:10.1109/ASAP.2014.6868647

Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip

Waqar Hussain
, Roberto Airoldi
, Henry Hoffmann
, Tapani Ahonen
, Jari Nurmi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

12 Citations (Scopus)

Translated title of the contribution	Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip
Original language	English
Title of host publication	2014 IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 18-20 June 2014, Zurich
Publisher	IEEE
Pages	131-138
Number of pages	8
ISBN (Electronic)	978-1-4799-3608-3
ISBN (Print)	978-1-4799-3609-0
DOIs	https://doi.org/10.1109/ASAP.2014.6868647
Publication status	Published - 2014
Publication type	A4 Article in conference proceedings
Event	International conference on application-specific systems, architectures and processors - Duration: 1 Jan 2014 → …

Conference

Conference	International conference on application-specific systems, architectures and processors
Period	1/01/14 → …

Publication forum classification

Publication forum level 1

Access to Document

10.1109/ASAP.2014.6868647

Cite this

Hussain, W., Airoldi, R., Hoffmann, H., Ahonen, T., & Nurmi, J. (2014). Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip. In 2014 IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 18-20 June 2014, Zurich (pp. 131-138). IEEE. https://doi.org/10.1109/ASAP.2014.6868647

@inproceedings{8fe4d936c9ad4f808a15dcf05e75e27b,

title = "Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip",

author = "Waqar Hussain and Roberto Airoldi and Henry Hoffmann and Tapani Ahonen and Jari Nurmi",

note = "Contribution: organisation=elt,FACT1=1<br/>Portfolio EDEND: 2014-08-30<br/>Publisher name: Institute of Electrical and Electronics Engineers IEEE; International conference on application-specific systems, architectures and processors ; Conference date: 01-01-2014",

year = "2014",

doi = "10.1109/ASAP.2014.6868647",

language = "English",

isbn = "978-1-4799-3609-0",

pages = "131--138",

booktitle = "2014 IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 18-20 June 2014, Zurich",

publisher = "IEEE",

address = "United States",

}

Hussain, W, Airoldi, R, Hoffmann, H, Ahonen, T & Nurmi, J 2014, Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip. in 2014 IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 18-20 June 2014, Zurich. IEEE, pp. 131-138, International conference on application-specific systems, architectures and processors, 1/01/14. https://doi.org/10.1109/ASAP.2014.6868647

Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip. / Hussain, Waqar; Airoldi, Roberto; Hoffmann, Henry et al.
2014 IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 18-20 June 2014, Zurich. IEEE, 2014. p. 131-138.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip

AU - Hussain, Waqar

AU - Airoldi, Roberto

AU - Hoffmann, Henry

AU - Ahonen, Tapani

AU - Nurmi, Jari

N1 - Contribution: organisation=elt,FACT1=1<br/>Portfolio EDEND: 2014-08-30<br/>Publisher name: Institute of Electrical and Electronics Engineers IEEE

PY - 2014

Y1 - 2014

U2 - 10.1109/ASAP.2014.6868647

DO - 10.1109/ASAP.2014.6868647

M3 - Conference contribution

SN - 978-1-4799-3609-0

SP - 131

EP - 138

BT - 2014 IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 18-20 June 2014, Zurich

PB - IEEE

T2 - International conference on application-specific systems, architectures and processors

Y2 - 1 January 2014

ER -

Hussain W, Airoldi R, Hoffmann H, Ahonen T, Nurmi J. Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip. In 2014 IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 18-20 June 2014, Zurich. IEEE. 2014. p. 131-138 doi: 10.1109/ASAP.2014.6868647