Abstract
Multimedia applications and embedded platforms are both becoming very complex in order to improve user experience. Thus, multimedia developers need high-level methods to automate time-consuming and error-prone tasks. Dynamic dataflow modeling is attractive to describe complex applications, such as video codecs, at a high level of abstraction. This paper presents a dataflow-based design approach to implement video codecs on embedded multi-core platforms. First, we introduce a custom architecture model to design low-power multi-core chips based on distributed memory and Transport-Triggered Architecture processor cores. Then, we describe software synthesis techniques to improve dynamic dataflow implementations. This methodology has been implemented into open-source tools and demonstrated on video decoders based on the MPEG-4 Visual standard and the new High Efficiency Video Coding standard. The simulations achieve real-time decoding (40FPS) of high definition (720P) MPEG-4 Visual video sequences on a custom multi-core platform clocked at 1Ghz, which is an improvement of more than 100 % over previously proposed implementations.
| Translated title of the contribution | Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs |
|---|---|
| Original language | English |
| Pages (from-to) | 121-136 |
| Number of pages | 16 |
| Journal | Journal of Signal Processing Systems |
| Volume | 80 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - Jun 2015 |
| Publication type | A1 Journal article-refereed |
Publication forum classification
- Publication forum level 1