Energy-Delay Trade-offs in Instruction Register File Design

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    2 Citations (Scopus)
    9 Downloads (Pure)


    In order to decrease latency and energy consumption, processors use hierarchical memory systems to store temporally and spatially related instructions close to the core. Instruction register file (IRF) is an energy-efficient solution for the lowest level in the instruction memory hierarchy. Being compiler-controlled, it removes the area and energy overheads involved in cache tag checking and adds flexibility in the separation of the instruction fetch and execution. In this paper, we systematically evaluate for the first time the effect of three IRF design variations on energy and delay against an unoptimized baseline IRF. Having instruction fetch and decode with IRF in the same pipeline stage allows minimal delay branching, but results in low operating clock frequency and impaired energy delay product compared to splitting them into two stages. Assuring instruction presence in IRF before execution with software reduces the area and increases maximum clock frequency compared to assurance with hardware, but requires compiler analysis. With a proposed compiler-analyzed instruction placement and co-designed hardware implementation, energy consumption with the best IRF variant is reduced by 9% on average with EEMBC Coremark and CHStone benchmaks. The energy delay product is improved by 23% when compared to the baseline IRF approach.
    Original languageEnglish
    Title of host publication2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
    ISBN (Electronic)978-1-5386-7656-1
    ISBN (Print)978-1-5386-7657-8
    Publication statusPublished - Oct 2018
    Publication typeA4 Article in conference proceedings
    EventIEEE Nordic Circuits and Systems Conference -
    Duration: 1 Jan 2000 → …


    ConferenceIEEE Nordic Circuits and Systems Conference
    Period1/01/00 → …


    • Energy efficiency
    • low power
    • Computer architecture
    • Instruction fetch

    Publication forum classification

    • Publication forum level 1

    ASJC Scopus subject areas

    • Hardware and Architecture


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