Abstract
Advanced Internet-of-Things applications require control-oriented codes to be executed with low latency for fast responsivity while their advanced signal processing and decision making tasks require computational capabilities. For this context, we propose three multi-issue core designs featuring an exposed datapath architecture with high performance, while retaining energy-efficiency. These features are achieved with exploitation of instruction-level parallelism, fast branching and the use of an instruction register file. With benchmarks in control-flow and signal processing application domains we measured in the best case 64% reduced energy consumption compared to a state-of-the-art RISC core, while consuming less silicon area. A high-performance design point reaches nearly 2.6 GHz operating frequency in the best case, over 2× improvement, while simultaneously achieving a 14% improvement in system energy-delay product.
Original language | English |
---|---|
Pages (from-to) | 1057–1073 |
Number of pages | 17 |
Journal | Journal of Signal Processing Systems |
Volume | 92 |
DOIs | |
Publication status | Published - 26 Jul 2020 |
Publication type | A1 Journal article-refereed |
Publication forum classification
- Publication forum level 1