ENEST - Efficient Interrupt Nesting for RISC-V based CPUs

Per Lindgren; Pawel Dzialo; Henri Lunnikivi; Johan Ericsson

doi:10.1109/ONCON60463.2023.10431132

ENEST - Efficient Interrupt Nesting for RISC-V based CPUs

Per Lindgren, Pawel Dzialo, Henri Lunnikivi, Johan Ericsson

Computing Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

Abstract

Embedded systems are typically driven by external and internal events, implemented by means of (static priority) interrupts. Response time can be improved by allowing for interrupt nesting, i.e., allowing for a higher priority interrupt to preempt the execution of a currently running interrupt handler. In this paper we study interrupt nesting for the RISC-V architecture and propose ENEST: a stacking approach with predictable overhead, minimizing both blocking and interference. Claims of the proposed mechanism are validated on the modern ESP32-C3 single core MCU. Our experimental results quantify blocking and interference, allowing further static scheduling analysis of ENEST based applications.

Original language	English
Title of host publication	2023 IEEE 2nd Industrial Electronics Society Annual On-Line Conference, ONCON 2023
Publisher	IEEE
Pages	1-7
ISBN (Electronic)	979-8-3503-5797-4
DOIs	https://doi.org/10.1109/ONCON60463.2023.10431132
Publication status	Published - 2023
Publication type	A4 Article in conference proceedings
Event	IEEE Industrial Electronics Society Annual On-Line Conference - Virtual, United States Duration: 8 Dec 2023 → 10 Dec 2023

Conference

Conference	IEEE Industrial Electronics Society Annual On-Line Conference
Country/Territory	United States
Period	8/12/23 → 10/12/23

Publication forum classification

Publication forum level 1

ASJC Scopus subject areas

Artificial Intelligence
Energy Engineering and Power Technology
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Control and Optimization

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10.1109/ONCON60463.2023.10431132

Cite this

@inproceedings{f6b348d0fc834a358d97f660788527ac,

title = "ENEST - Efficient Interrupt Nesting for RISC-V based CPUs",

abstract = "Embedded systems are typically driven by external and internal events, implemented by means of (static priority) interrupts. Response time can be improved by allowing for interrupt nesting, i.e., allowing for a higher priority interrupt to preempt the execution of a currently running interrupt handler. In this paper we study interrupt nesting for the RISC-V architecture and propose ENEST: a stacking approach with predictable overhead, minimizing both blocking and interference. Claims of the proposed mechanism are validated on the modern ESP32-C3 single core MCU. Our experimental results quantify blocking and interference, allowing further static scheduling analysis of ENEST based applications.",

author = "Per Lindgren and Pawel Dzialo and Henri Lunnikivi and Johan Ericsson",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; IEEE Industrial Electronics Society Annual On-Line Conference ; Conference date: 08-12-2023 Through 10-12-2023",

year = "2023",

doi = "10.1109/ONCON60463.2023.10431132",

language = "English",

pages = "1--7",

booktitle = "2023 IEEE 2nd Industrial Electronics Society Annual On-Line Conference, ONCON 2023",

publisher = "IEEE",

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TY - GEN

T1 - ENEST - Efficient Interrupt Nesting for RISC-V based CPUs

AU - Lindgren, Per

AU - Dzialo, Pawel

AU - Lunnikivi, Henri

AU - Ericsson, Johan

PY - 2023

Y1 - 2023

N2 - Embedded systems are typically driven by external and internal events, implemented by means of (static priority) interrupts. Response time can be improved by allowing for interrupt nesting, i.e., allowing for a higher priority interrupt to preempt the execution of a currently running interrupt handler. In this paper we study interrupt nesting for the RISC-V architecture and propose ENEST: a stacking approach with predictable overhead, minimizing both blocking and interference. Claims of the proposed mechanism are validated on the modern ESP32-C3 single core MCU. Our experimental results quantify blocking and interference, allowing further static scheduling analysis of ENEST based applications.

AB - Embedded systems are typically driven by external and internal events, implemented by means of (static priority) interrupts. Response time can be improved by allowing for interrupt nesting, i.e., allowing for a higher priority interrupt to preempt the execution of a currently running interrupt handler. In this paper we study interrupt nesting for the RISC-V architecture and propose ENEST: a stacking approach with predictable overhead, minimizing both blocking and interference. Claims of the proposed mechanism are validated on the modern ESP32-C3 single core MCU. Our experimental results quantify blocking and interference, allowing further static scheduling analysis of ENEST based applications.

U2 - 10.1109/ONCON60463.2023.10431132

DO - 10.1109/ONCON60463.2023.10431132

M3 - Conference contribution

AN - SCOPUS:85186748270

SP - 1

EP - 7

BT - 2023 IEEE 2nd Industrial Electronics Society Annual On-Line Conference, ONCON 2023

PB - IEEE

T2 - IEEE Industrial Electronics Society Annual On-Line Conference

Y2 - 8 December 2023 through 10 December 2023

ER -

ENEST - Efficient Interrupt Nesting for RISC-V based CPUs

Abstract

Conference

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ASJC Scopus subject areas

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Cite this