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Evaluation of Coarse-Grained Reconfigurable Array for a Dual Mode OTFS-OFDM Modulator

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

3 Citations (Scopus)
14 Downloads (Pure)

Abstract

Orthogonal Time Frequency Space (OTFS) multiplexing, a prospective waveform for 6G offers high reliability under high mobility compared to Orthogonal Frequency Division Multiplexing (OFDM), but it is characterized by relatively high computational complexity. To address this challenge, a dual-mode framework has been proposed in the literature that dynamically switches between OFDM and OTFS as needed. However, processing such a computationally intensive workload is not feasible on general-purpose processors and therefore must be accelerated through an Application-Specific Integrated Circuit (ASIC) or a reconfigurable hardware device. A typical form of a reconfigurable hardware is a Coarse-Grained Reconfigurable Array (CGRA). The concept of CGRA has existed for a few decades, but it is still gaining traction due to its massively parallel processing capabilities and run-time reconfigurability. This paper proposes a CGRA-based modulator to meet the run-time switching requirements for a dual-mode OFDM-OTFS system. The CGRA is synthesized on a Stratix-IV FPGA device for prototyping purposes. Operating at a frequency of 181.0 MHz, the CGRA delivers a performance of 11.58 GOPS with a dynamic power dissipation of 308 mW. The proposed architecture is evaluated for multiple OTFS scales (8 × 4,8× 8,16× 16) and demonstrates that the proposed solution offers promising results in terms of both performance and scalability.

Original languageEnglish
Title of host publicationProceedings - 2024 IEEE Workshop on Signal Processing Systems, SiPS 2024
PublisherIEEE
Pages183-188
Number of pages6
ISBN (Electronic)9798350373752
ISBN (Print)9798350373769
DOIs
Publication statusPublished - 2024
Publication typeA4 Article in conference proceedings
EventIEEE Workshop on Signal Processing Systems - Cambridge, United States
Duration: 4 Nov 20246 Nov 2024

Publication series

NameIEEE International Workshop on Signal Processing Systems
ISSN (Print)1520-6130
ISSN (Electronic)2374-7390

Conference

ConferenceIEEE Workshop on Signal Processing Systems
Country/TerritoryUnited States
CityCambridge
Period4/11/246/11/24

Funding

This work was supported by the doctoral grants of the Faculty of Information Technology and Communication Sciences at Tampere University.

Funders
Faculty of Information Technology and Communication Sciences, Tampere University

    Keywords

    • 2D FFT
    • 6G
    • CGRA
    • Gear-box PHY
    • OFDM
    • OTFS
    • Reconfigurable Computing

    Publication forum classification

    • Publication forum level 1

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Signal Processing
    • Applied Mathematics
    • Hardware and Architecture

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