Fault-tolerant 2-D mesh network-on-chip for multi-processor systems-on-chip

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    Translated title of the contributionFault-tolerant 2-D mesh network-on-chip for multi-processor systems-on-chip
    Original languageEnglish
    Title of host publicationProceedings of 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 18-21 April, 2006, Prague, Czech Republic
    EditorsM.S. Reorda
    Pages186-190
    Publication statusPublished - 2006
    Publication typeA4 Article in conference proceedings

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