Feasibility of FPGA accelerated IPsec on cloud

Markku Vajaranta; Vili Viitamäki; Arto Oinonen; Timo D. Hämäläinen; Ari Kulmala; Jouni Markunmäki

doi:10.1109/DSD.2018.00099

Feasibility of FPGA accelerated IPsec on cloud

Markku Vajaranta, Vili Viitamäki, Arto Oinonen, Timo D. Hämäläinen, Ari Kulmala, Jouni Markunmäki

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

5 Citations (Scopus)

Abstract

Line-rate speed requirements for performance hungry network applications like IPsec are getting problematic due to the virtualization trend. A single virtual network application hardly can provide 40 Gbps operation. This research considers the IPsec packet processing without IKE to be offloaded on an FPGA in a network. We propose an IPsec accelerator in an FPGA and explain the details that need to be considered for a production ready design. Based on our evaluation, Intel Arria 10 FPGA can provide 10 Gbps line-rate operation for the IPsec accelerator and to be responsible for 1000 IPsec tunnels. The research points out that for future data centers it is beneficial to rely on HW acceleration in terms of speed and energy efficiency for applications like IPsec.

Original language	English
Title of host publication	2018 Euromicro Conference on Digital System Design (DSD)
Publisher	IEEE
ISBN (Electronic)	978-1-5386-7377-5
DOIs	https://doi.org/10.1109/DSD.2018.00099
Publication status	Published - 31 Aug 2018
Publication type	A4 Article in conference proceedings
Event	Euromicro Conference on Digital System Design - Prague, Czech Republic Duration: 29 Aug 2018 → 31 Aug 2018

Conference

Conference	Euromicro Conference on Digital System Design
Country/Territory	Czech Republic
City	Prague
Period	29/08/18 → 31/08/18

Publication forum classification

Publication forum level 1

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/DSD.2018.00099

Cite this

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title = "Feasibility of FPGA accelerated IPsec on cloud",

abstract = "Line-rate speed requirements for performance hungry network applications like IPsec are getting problematic due to the virtualization trend. A single virtual network application hardly can provide 40 Gbps operation. This research considers the IPsec packet processing without IKE to be offloaded on an FPGA in a network. We propose an IPsec accelerator in an FPGA and explain the details that need to be considered for a production ready design. Based on our evaluation, Intel Arria 10 FPGA can provide 10 Gbps line-rate operation for the IPsec accelerator and to be responsible for 1000 IPsec tunnels. The research points out that for future data centers it is beneficial to rely on HW acceleration in terms of speed and energy efficiency for applications like IPsec.",

author = "Markku Vajaranta and Vili Viitam{\"a}ki and Arto Oinonen and H{\"a}m{\"a}l{\"a}inen, {Timo D.} and Ari Kulmala and Jouni Markunm{\"a}ki",

year = "2018",

month = aug,

day = "31",

doi = "10.1109/DSD.2018.00099",

language = "English",

booktitle = "2018 Euromicro Conference on Digital System Design (DSD)",

publisher = "IEEE",

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T1 - Feasibility of FPGA accelerated IPsec on cloud

AU - Vajaranta, Markku

AU - Viitamäki, Vili

AU - Oinonen, Arto

AU - Hämäläinen, Timo D.

AU - Kulmala, Ari

AU - Markunmäki, Jouni

PY - 2018/8/31

Y1 - 2018/8/31

N2 - Line-rate speed requirements for performance hungry network applications like IPsec are getting problematic due to the virtualization trend. A single virtual network application hardly can provide 40 Gbps operation. This research considers the IPsec packet processing without IKE to be offloaded on an FPGA in a network. We propose an IPsec accelerator in an FPGA and explain the details that need to be considered for a production ready design. Based on our evaluation, Intel Arria 10 FPGA can provide 10 Gbps line-rate operation for the IPsec accelerator and to be responsible for 1000 IPsec tunnels. The research points out that for future data centers it is beneficial to rely on HW acceleration in terms of speed and energy efficiency for applications like IPsec.

AB - Line-rate speed requirements for performance hungry network applications like IPsec are getting problematic due to the virtualization trend. A single virtual network application hardly can provide 40 Gbps operation. This research considers the IPsec packet processing without IKE to be offloaded on an FPGA in a network. We propose an IPsec accelerator in an FPGA and explain the details that need to be considered for a production ready design. Based on our evaluation, Intel Arria 10 FPGA can provide 10 Gbps line-rate operation for the IPsec accelerator and to be responsible for 1000 IPsec tunnels. The research points out that for future data centers it is beneficial to rely on HW acceleration in terms of speed and energy efficiency for applications like IPsec.

U2 - 10.1109/DSD.2018.00099

DO - 10.1109/DSD.2018.00099

M3 - Conference contribution

BT - 2018 Euromicro Conference on Digital System Design (DSD)

PB - IEEE

T2 - Euromicro Conference on Digital System Design

Y2 - 29 August 2018 through 31 August 2018

ER -

Feasibility of FPGA accelerated IPsec on cloud

Abstract

Conference

Publication forum classification

UN SDGs

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