FPGA-Powered 4K120p HEVC Intra Encoder

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    This paper presents a hardware-accelerated Kvazaar HEVC intra encoder for 4K real-time video coding at up to 120 fps. The encoder is implemented on a Nokia AirFrame Cloud Server featuring a 2.4 GHz dual 14-core Intel Xeon processor and two Arria 10 PCI Express FPGA accelerator cards. The presented encoder is a speed-optimized version of our 1st generation 4K40p HEVC intra encoder. The proposed speedup techniques include 1) Increasing the number of FPGA cards to two; 2) Remapping the simplest multiplications from DSP blocks to logic for better FPGA utilization; 3) Making task scheduling more flexible to improve utilization rate of hardware accelerators; and 4) Increasing the pipeline depth and duplicating time-sensitive resources in the hardware accelerator. As a result, up to three hardware accelerator instances can be accommodated in a single Arria 10 so the encoder is able to make use of six accelerators. According to our experiments, the proposed encoder obtains threefold speedup over our 1st generation encoder. Our proposal is also shown to outperform all other encountered FPGA and ASIC implementations.
    Original languageEnglish
    Title of host publication2018 IEEE International Symposium on Circuits and Systems (ISCAS)
    ISBN (Electronic)978-1-5386-4881-0
    Publication statusPublished - 2018
    Publication typeA4 Article in conference proceedings
    EventIEEE International Symposium on Circuits and Systems - Florence, Italy
    Duration: 27 May 201830 May 2018

    Publication series

    ISSN (Electronic)2379-447X


    ConferenceIEEE International Symposium on Circuits and Systems

    Publication forum classification

    • Publication forum level 1


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