Hierarchical integrated VLSI simulation environment - Device parameter optimization for circuit simulation

P. Ojala, K. Kaski, J. Poutala, K. Kankaala, H. Tenhunen

Research output: Book/Report › Commissioned report

Translated title of the contribution	Hierarchical integrated VLSI simulation environment - Device parameter optimization for circuit simulation
Original language	English
Place of Publication	Tampere
Publisher	Tampere University of Technology
Number of pages	40
Publication status	Published - 1989
Publication type	D4 Published development or research report or study

Name	TUT/Electronics Laboratory, Report
Publisher	Tampere University of Technology
No.	5

Publication forum classification

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title = "Hierarchical integrated VLSI simulation environment - Device parameter optimization for circuit simulation",

author = "P. Ojala and K. Kaski and J. Poutala and K. Kankaala and H. Tenhunen",

note = "Contribution: organisation=ele,FACT1=1",

year = "1989",

language = "English",

series = "TUT/Electronics Laboratory, Report",

publisher = "Tampere University of Technology",

number = "5",

}

TY - BOOK

T1 - Hierarchical integrated VLSI simulation environment - Device parameter optimization for circuit simulation

AU - Ojala, P.

AU - Kaski, K.

AU - Poutala, J.

AU - Kankaala, K.

AU - Tenhunen, H.

N1 - Contribution: organisation=ele,FACT1=1

PY - 1989

Y1 - 1989

M3 - Commissioned report

T3 - TUT/Electronics Laboratory, Report

BT - Hierarchical integrated VLSI simulation environment - Device parameter optimization for circuit simulation

PB - Tampere University of Technology

CY - Tampere

ER -