High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA

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    Abstract

    This paper presents a High-Level Synthesis (HLS) flow for mapping a software HEVC encoder into Altera CycloneV SoC-FPGA. The starting point is a C
    implementation of an open-source Kvazaar HEVC intra encoder, which is minimally refined for SystemC design space exploration and automatic Catapult-C RTL generation. The final implementation involves Kvazaar encoder executed in Linux on dual-core ARM, and HW accelerated intra prediction
    on FPGA. Changing the SW/HW partitioning or modifying the implementation takes hours instead of weeks with Catapult-C HLS. In addition, the design is portable to other platforms without major manual re-writing. We obtained 9 fps full-HD intra prediction speed with a single accelerator on Altera Cyclone V SX on Terasic VEEK-MT-C5SoC board including video capture and HEVC video streaming via Ethernet. To the best of our knowledge, this is the first reported HLS assisted implementation of HEVC encoder on SoC-FPGA.
    Original languageEnglish
    Title of host publication18th Euromicro Conference on Digital Systems Design (DSD 2015)
    PublisherIEEE
    Pages49 - 56
    Number of pages8
    ISBN (Print)978-1-4673-8035-5
    DOIs
    Publication statusPublished - 2015
    Publication typeA4 Article in a conference publication
    EventEuromicro Conference on Digital System Design -
    Duration: 1 Jan 1900 → …

    Conference

    ConferenceEuromicro Conference on Digital System Design
    Period1/01/00 → …

    Keywords

    • High-Level Synthesis
    • C to RTL
    • Catapult-C
    • HEVC
    • Kvazaar
    • intra coding
    • SoC-FPGA
    • SystemC
    • Cyclone V

    Publication forum classification

    • Publication forum level 1

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