High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA

Panu Sjövall; Janne Virtanen; Jarno Vanne; Timo D. Hämäläinen

doi:10.1109/DSD.2015.67

High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA

Panu Sjövall, Janne Virtanen, Jarno Vanne, Timo D. Hämäläinen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

19 Citations (Scopus)

Abstract

This paper presents a High-Level Synthesis (HLS) flow for mapping a software HEVC encoder into Altera CycloneV SoC-FPGA. The starting point is a C
implementation of an open-source Kvazaar HEVC intra encoder, which is minimally refined for SystemC design space exploration and automatic Catapult-C RTL generation. The final implementation involves Kvazaar encoder executed in Linux on dual-core ARM, and HW accelerated intra prediction
on FPGA. Changing the SW/HW partitioning or modifying the implementation takes hours instead of weeks with Catapult-C HLS. In addition, the design is portable to other platforms without major manual re-writing. We obtained 9 fps full-HD intra prediction speed with a single accelerator on Altera Cyclone V SX on Terasic VEEK-MT-C5SoC board including video capture and HEVC video streaming via Ethernet. To the best of our knowledge, this is the first reported HLS assisted implementation of HEVC encoder on SoC-FPGA.

Original language	English
Title of host publication	18th Euromicro Conference on Digital Systems Design (DSD 2015)
Publisher	IEEE
Pages	49 - 56
Number of pages	8
ISBN (Print)	978-1-4673-8035-5
DOIs	https://doi.org/10.1109/DSD.2015.67
Publication status	Published - 2015
Publication type	A4 Article in conference proceedings
Event	Euromicro Conference on Digital System Design - Duration: 1 Jan 1900 → …

Conference

Conference	Euromicro Conference on Digital System Design
Period	1/01/00 → …

Keywords

High-Level Synthesis
C to RTL
Catapult-C
HEVC
Kvazaar
intra coding
SoC-FPGA
SystemC
Cyclone V

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@inproceedings{da709a587500489ca9d3f45e788dc9d2,

title = "High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA",

abstract = "This paper presents a High-Level Synthesis (HLS) flow for mapping a software HEVC encoder into Altera CycloneV SoC-FPGA. The starting point is a C implementation of an open-source Kvazaar HEVC intra encoder, which is minimally refined for SystemC design space exploration and automatic Catapult-C RTL generation. The final implementation involves Kvazaar encoder executed in Linux on dual-core ARM, and HW accelerated intra prediction on FPGA. Changing the SW/HW partitioning or modifying the implementation takes hours instead of weeks with Catapult-C HLS. In addition, the design is portable to other platforms without major manual re-writing. We obtained 9 fps full-HD intra prediction speed with a single accelerator on Altera Cyclone V SX on Terasic VEEK-MT-C5SoC board including video capture and HEVC video streaming via Ethernet. To the best of our knowledge, this is the first reported HLS assisted implementation of HEVC encoder on SoC-FPGA. ",

keywords = "High-Level Synthesis, C to RTL, Catapult-C, HEVC, Kvazaar, intra coding, SoC-FPGA, SystemC, Cyclone V",

author = "Panu Sj{\"o}vall and Janne Virtanen and Jarno Vanne and H{\"a}m{\"a}l{\"a}inen, \{Timo D.\}",

year = "2015",

doi = "10.1109/DSD.2015.67",

language = "English",

isbn = "978-1-4673-8035-5",

pages = "49 -- 56",

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TY - GEN

T1 - High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA

AU - Sjövall, Panu

AU - Virtanen, Janne

AU - Vanne, Jarno

AU - Hämäläinen, Timo D.

PY - 2015

Y1 - 2015

N2 - This paper presents a High-Level Synthesis (HLS) flow for mapping a software HEVC encoder into Altera CycloneV SoC-FPGA. The starting point is a C implementation of an open-source Kvazaar HEVC intra encoder, which is minimally refined for SystemC design space exploration and automatic Catapult-C RTL generation. The final implementation involves Kvazaar encoder executed in Linux on dual-core ARM, and HW accelerated intra prediction on FPGA. Changing the SW/HW partitioning or modifying the implementation takes hours instead of weeks with Catapult-C HLS. In addition, the design is portable to other platforms without major manual re-writing. We obtained 9 fps full-HD intra prediction speed with a single accelerator on Altera Cyclone V SX on Terasic VEEK-MT-C5SoC board including video capture and HEVC video streaming via Ethernet. To the best of our knowledge, this is the first reported HLS assisted implementation of HEVC encoder on SoC-FPGA.

AB - This paper presents a High-Level Synthesis (HLS) flow for mapping a software HEVC encoder into Altera CycloneV SoC-FPGA. The starting point is a C implementation of an open-source Kvazaar HEVC intra encoder, which is minimally refined for SystemC design space exploration and automatic Catapult-C RTL generation. The final implementation involves Kvazaar encoder executed in Linux on dual-core ARM, and HW accelerated intra prediction on FPGA. Changing the SW/HW partitioning or modifying the implementation takes hours instead of weeks with Catapult-C HLS. In addition, the design is portable to other platforms without major manual re-writing. We obtained 9 fps full-HD intra prediction speed with a single accelerator on Altera Cyclone V SX on Terasic VEEK-MT-C5SoC board including video capture and HEVC video streaming via Ethernet. To the best of our knowledge, this is the first reported HLS assisted implementation of HEVC encoder on SoC-FPGA.

KW - High-Level Synthesis

KW - C to RTL

KW - Catapult-C

KW - HEVC

KW - Kvazaar

KW - intra coding

KW - SoC-FPGA

KW - SystemC

KW - Cyclone V

U2 - 10.1109/DSD.2015.67

DO - 10.1109/DSD.2015.67

M3 - Conference contribution

SN - 978-1-4673-8035-5

SP - 49

EP - 56

BT - 18th Euromicro Conference on Digital Systems Design (DSD 2015)

PB - IEEE

T2 - Euromicro Conference on Digital System Design

Y2 - 1 January 1900

ER -

High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA

Abstract

Conference

Keywords

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