High-level synthesis implementation of transform-exempted SATD architectures for low-power video coding

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Abstract

This paper presents the first known high-level synthesis (HLS) implementation for the Sum of Absolute Transformed Differences (SATD) calculation. The proposed hardware architecture is designed for two SATD algorithms: a widespread Fast Walsh-Hadamard Transform (FWHT-SATD) and a recently introduced Transform Exempted scheme (TE-SATD). This 2-stage architecture is made up of two 1-D Walsh-Hadamard Transform (WHT) stages and a transpose buffer (TB) between them. The chosen HLS approach cuts down design time over contemporary design methods and thereby made it feasible to implement a set of dedicated FWHT-SATD and TE-SATD architectures for 4×4, 8×8, and 16×16 pixel blocks. All these six architectures were synthesized for 28 nm and 45 nm standard cell technologies, and their area and energy consumptions were analysed. TE-based implementations provide 6.0-8.3% total cell area savings and 6.9-12.7% better energy-efficiency than traditional FWHT approaches. Our proposal is the first to introduce TE-SATD architectures for up to 16×16 blocks and each of these tailored architectures was shown to provide better trade-off between silicon area and performance than their reference implementations.

Original languageEnglish
Title of host publication2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
PublisherIEEE
Number of pages5
ISBN (Print)9781728192017
DOIs
Publication statusPublished - 2021
Publication typeA4 Article in a conference publication
EventIEEE International Symposium on Circuits and Systems - Daegu, Korea, Republic of
Duration: 22 May 202128 May 2021

Publication series

NameIEEE International Symposium on Circuits and Systems proceedings
ISSN (Print)0271-4302
ISSN (Electronic)2158-1525

Conference

ConferenceIEEE International Symposium on Circuits and Systems
Country/TerritoryKorea, Republic of
CityDaegu
Period22/05/2128/05/21

Keywords

  • Hadamard transform
  • High-level synthesis (HLS)
  • Low-power hardware design
  • Sum of absolute transformed differences (SATD)
  • Video coding

Publication forum classification

  • Publication forum level 1

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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