High-level synthesis implementation of transform-exempted SATD architectures for low-power video coding

Tero Partanen; Ari Lemmetti; Panu Sjövall; Jarno Vanne

doi:10.1109/ISCAS51556.2021.9401399

High-level synthesis implementation of transform-exempted SATD architectures for low-power video coding

Computing Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

2 Citations (Scopus)

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Abstract

This paper presents the first known high-level synthesis (HLS) implementation for the Sum of Absolute Transformed Differences (SATD) calculation. The proposed hardware architecture is designed for two SATD algorithms: a widespread Fast Walsh-Hadamard Transform (FWHT-SATD) and a recently introduced Transform Exempted scheme (TE-SATD). This 2-stage architecture is made up of two 1-D Walsh-Hadamard Transform (WHT) stages and a transpose buffer (TB) between them. The chosen HLS approach cuts down design time over contemporary design methods and thereby made it feasible to implement a set of dedicated FWHT-SATD and TE-SATD architectures for 4×4, 8×8, and 16×16 pixel blocks. All these six architectures were synthesized for 28 nm and 45 nm standard cell technologies, and their area and energy consumptions were analysed. TE-based implementations provide 6.0-8.3% total cell area savings and 6.9-12.7% better energy-efficiency than traditional FWHT approaches. Our proposal is the first to introduce TE-SATD architectures for up to 16×16 blocks and each of these tailored architectures was shown to provide better trade-off between silicon area and performance than their reference implementations.

Original language	English
Title of host publication	2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
Publisher	IEEE
Number of pages	5
ISBN (Print)	9781728192017
DOIs	https://doi.org/10.1109/ISCAS51556.2021.9401399
Publication status	Published - 2021
Publication type	A4 Article in conference proceedings
Event	IEEE International Symposium on Circuits and Systems - Daegu, Korea, Republic of Duration: 22 May 2021 → 28 May 2021

Publication series

Name	IEEE International Symposium on Circuits and Systems proceedings
ISSN (Print)	0271-4302
ISSN (Electronic)	2158-1525

Conference

Conference	IEEE International Symposium on Circuits and Systems
Country/Territory	Korea, Republic of
City	Daegu
Period	22/05/21 → 28/05/21

Funding

This work was supported in part by the European ECSEL project ADACORSA (under the grant agreement 876019).

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Hadamard transform
High-level synthesis (HLS)
Low-power hardware design
Sum of absolute transformed differences (SATD)
Video coding

Publication forum classification

Publication forum level 1

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ISCAS51556.2021.9401399

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http://urn.fi/URN:NBN:fi:tuni-202109107044

Cite this

Partanen, T., Lemmetti, A., Sjövall, P., & Vanne, J. (2021). High-level synthesis implementation of transform-exempted SATD architectures for low-power video coding. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings Article 9401399 (IEEE International Symposium on Circuits and Systems proceedings). IEEE. https://doi.org/10.1109/ISCAS51556.2021.9401399

@inproceedings{c64f5ecff8df48f6bc371fa826c99b95,

title = "High-level synthesis implementation of transform-exempted SATD architectures for low-power video coding",

abstract = "This paper presents the first known high-level synthesis (HLS) implementation for the Sum of Absolute Transformed Differences (SATD) calculation. The proposed hardware architecture is designed for two SATD algorithms: a widespread Fast Walsh-Hadamard Transform (FWHT-SATD) and a recently introduced Transform Exempted scheme (TE-SATD). This 2-stage architecture is made up of two 1-D Walsh-Hadamard Transform (WHT) stages and a transpose buffer (TB) between them. The chosen HLS approach cuts down design time over contemporary design methods and thereby made it feasible to implement a set of dedicated FWHT-SATD and TE-SATD architectures for 4×4, 8×8, and 16×16 pixel blocks. All these six architectures were synthesized for 28 nm and 45 nm standard cell technologies, and their area and energy consumptions were analysed. TE-based implementations provide 6.0-8.3\% total cell area savings and 6.9-12.7\% better energy-efficiency than traditional FWHT approaches. Our proposal is the first to introduce TE-SATD architectures for up to 16×16 blocks and each of these tailored architectures was shown to provide better trade-off between silicon area and performance than their reference implementations.",

keywords = "Hadamard transform, High-level synthesis (HLS), Low-power hardware design, Sum of absolute transformed differences (SATD), Video coding",

author = "Tero Partanen and Ari Lemmetti and Panu Sj{\"o}vall and Jarno Vanne",

note = "JUFOID=65438 Funding Information: This work was supported in part by the European ECSEL project ADACORSA (under the grant agreement 876019). Publisher Copyright: {\textcopyright} 2021 IEEE; IEEE International Symposium on Circuits and Systems ; Conference date: 22-05-2021 Through 28-05-2021",

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doi = "10.1109/ISCAS51556.2021.9401399",

language = "English",

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Partanen, T, Lemmetti, A, Sjövall, P & Vanne, J 2021, High-level synthesis implementation of transform-exempted SATD architectures for low-power video coding. in 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings., 9401399, IEEE International Symposium on Circuits and Systems proceedings, IEEE, IEEE International Symposium on Circuits and Systems, Daegu, Korea, Republic of, 22/05/21. https://doi.org/10.1109/ISCAS51556.2021.9401399

High-level synthesis implementation of transform-exempted SATD architectures for low-power video coding. / Partanen, Tero; Lemmetti, Ari; Sjövall, Panu et al.
2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. IEEE, 2021. 9401399 (IEEE International Symposium on Circuits and Systems proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

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T1 - High-level synthesis implementation of transform-exempted SATD architectures for low-power video coding

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AU - Lemmetti, Ari

AU - Sjövall, Panu

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PY - 2021

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N2 - This paper presents the first known high-level synthesis (HLS) implementation for the Sum of Absolute Transformed Differences (SATD) calculation. The proposed hardware architecture is designed for two SATD algorithms: a widespread Fast Walsh-Hadamard Transform (FWHT-SATD) and a recently introduced Transform Exempted scheme (TE-SATD). This 2-stage architecture is made up of two 1-D Walsh-Hadamard Transform (WHT) stages and a transpose buffer (TB) between them. The chosen HLS approach cuts down design time over contemporary design methods and thereby made it feasible to implement a set of dedicated FWHT-SATD and TE-SATD architectures for 4×4, 8×8, and 16×16 pixel blocks. All these six architectures were synthesized for 28 nm and 45 nm standard cell technologies, and their area and energy consumptions were analysed. TE-based implementations provide 6.0-8.3% total cell area savings and 6.9-12.7% better energy-efficiency than traditional FWHT approaches. Our proposal is the first to introduce TE-SATD architectures for up to 16×16 blocks and each of these tailored architectures was shown to provide better trade-off between silicon area and performance than their reference implementations.

AB - This paper presents the first known high-level synthesis (HLS) implementation for the Sum of Absolute Transformed Differences (SATD) calculation. The proposed hardware architecture is designed for two SATD algorithms: a widespread Fast Walsh-Hadamard Transform (FWHT-SATD) and a recently introduced Transform Exempted scheme (TE-SATD). This 2-stage architecture is made up of two 1-D Walsh-Hadamard Transform (WHT) stages and a transpose buffer (TB) between them. The chosen HLS approach cuts down design time over contemporary design methods and thereby made it feasible to implement a set of dedicated FWHT-SATD and TE-SATD architectures for 4×4, 8×8, and 16×16 pixel blocks. All these six architectures were synthesized for 28 nm and 45 nm standard cell technologies, and their area and energy consumptions were analysed. TE-based implementations provide 6.0-8.3% total cell area savings and 6.9-12.7% better energy-efficiency than traditional FWHT approaches. Our proposal is the first to introduce TE-SATD architectures for up to 16×16 blocks and each of these tailored architectures was shown to provide better trade-off between silicon area and performance than their reference implementations.

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KW - Video coding

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DO - 10.1109/ISCAS51556.2021.9401399

M3 - Conference contribution

AN - SCOPUS:85108999723

SN - 9781728192017

T3 - IEEE International Symposium on Circuits and Systems proceedings

BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings

PB - IEEE

T2 - IEEE International Symposium on Circuits and Systems

Y2 - 22 May 2021 through 28 May 2021

ER -

High-level synthesis implementation of transform-exempted SATD architectures for low-power video coding

Abstract

Publication series

Conference

Funding

UN SDGs

Keywords

Publication forum classification

ASJC Scopus subject areas

Access to Document

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Cite this