@inproceedings{0708758b84b84a0c8a5877691ed95922,
title = "High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA",
abstract = "This paper presents efficient inverse discrete cosine transform (IDCT) and inverse discrete sine transform (IDST) implementations for High Efficiency Video Coding (HEVC). The proposal makes use of high-level synthesis (HLS) to implement a complete HEVC 2-D IDCT/IDST architecture directly from the C code of a well-known Even-Odd decomposition algorithm. The final architecture includes a 4-point IDCT/IDST unit for the smallest transform blocks (TB), an 8/16/32-point IDCT unit for the other TBs, and a transpose memory for intermediate results. On Arria II FPGA, it supports real-time (60 fps) HEVC decoding of up to 2160p format with 12.4 kALUTs and 344 DSP blocks. Compared with the other existing HLS approach, the proposed solution is almost 5 times faster and is able to utilize available FPGA resources better.",
author = "Vili Viitam{\"a}ki and Panu Sj{\"o}vall and Jarno Vanne and H{\"a}m{\"a}l{\"a}inen, {Timo D.}",
note = "jufoid=57409; IEEE International Symposium on Circuits and Systems ; Conference date: 01-01-1900",
year = "2017",
doi = "10.1109/ISCAS.2017.8050323",
language = "English",
publisher = "IEEE",
pages = "1--4",
booktitle = "Proceedings of 2017 IEEE International Symposium on Circuits and Systems",
}