Implementation of a Nonlinear Self-Interference Canceller using High-Level Synthesis

Sakari Lahti; Timo Hämäläinen; Pablo Pascual Campo; Lauri Anttila; Mikko Valkama; Vesa Lampu

doi:10.1109/ISCAS45731.2020.9181183

Implementation of a Nonlinear Self-Interference Canceller using High-Level Synthesis

Sakari Lahti, Timo Hämäläinen, Pablo Pascual Campo, Lauri Anttila, Mikko Valkama, Vesa Lampu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

3 Citations (Scopus)

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Abstract

High-level synthesis (HLS) aims to improve the productivity of digital logic design over traditional register-transfer level (RTL) methods. This paper shows that HLS can replace RTL when implementing a complex data path oriented signal processing algorithm under strict throughput constraints. Our system is a nonlinear spline-based Hammerstein self-interference (SI) canceller for full-duplex transceiver capable of achieving high SI suppression, while maintaining low computational complexity. The achieved suppression of the SI is superb 45 dB, while consuming 29 026 of the available LUTs, 17992 of registers, and 655 of the DSP slices on Kintex-7 XC7K410T FPGA. Our paper also compares the usability of two commercial HLS tools that were used in this work.

Original language	English
Title of host publication	2020 IEEE International Symposium on Circuits and Systems (ISCAS)
Place of Publication	Sevilla
Publisher	IEEE
Pages	1-5
Number of pages	5
ISBN (Electronic)	978-1-7281-3320-1
DOIs	https://doi.org/10.1109/ISCAS45731.2020.9181183
Publication status	Published - 21 Oct 2020
Publication type	A4 Article in conference proceedings
Event	IEEE International Symposium on Circuits and Systems - Sevilla, Spain Duration: 10 Oct 2020 → 21 Oct 2020 https://iscas2020.org/

Conference

Conference	IEEE International Symposium on Circuits and Systems
Abbreviated title	ISCAS 2020
Country/Territory	Spain
City	Sevilla
Period	10/10/20 → 21/10/20
Internet address	https://iscas2020.org/

Keywords

Field Programmable Gate Array (FPGA)
Transceivers
Radio frequency
Full-duplex
High-Level Synthesis
Self-interference cancellation

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10.1109/ISCAS45731.2020.9181183

Implementation of a Nonlinear 2020
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Accepted author manuscript, 729 KB

http://urn.fi/URN:NBN:fi:tuni-202101201537

Cite this

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title = "Implementation of a Nonlinear Self-Interference Canceller using High-Level Synthesis",

abstract = "High-level synthesis (HLS) aims to improve the productivity of digital logic design over traditional register-transfer level (RTL) methods. This paper shows that HLS can replace RTL when implementing a complex data path oriented signal processing algorithm under strict throughput constraints. Our system is a nonlinear spline-based Hammerstein self-interference (SI) canceller for full-duplex transceiver capable of achieving high SI suppression, while maintaining low computational complexity. The achieved suppression of the SI is superb 45 dB, while consuming 29 026 of the available LUTs, 17992 of registers, and 655 of the DSP slices on Kintex-7 XC7K410T FPGA. Our paper also compares the usability of two commercial HLS tools that were used in this work.",

keywords = "Field Programmable Gate Array (FPGA), Transceivers, Radio frequency, Full-duplex, High-Level Synthesis, Self-interference cancellation",

author = "Sakari Lahti and Timo H{\"a}m{\"a}l{\"a}inen and {Pascual Campo}, Pablo and Lauri Anttila and Mikko Valkama and Vesa Lampu",

year = "2020",

month = oct,

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doi = "10.1109/ISCAS45731.2020.9181183",

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pages = "1--5",

booktitle = "2020 IEEE International Symposium on Circuits and Systems (ISCAS)",

publisher = "IEEE",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems, ISCAS 2020 ; Conference date: 10-10-2020 Through 21-10-2020",

url = "https://iscas2020.org/",

}

Lahti, S , Hämäläinen, T, Pascual Campo, P, Anttila, L , Valkama, M & Lampu, V 2020, Implementation of a Nonlinear Self-Interference Canceller using High-Level Synthesis. in 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, Sevilla, pp. 1-5, IEEE International Symposium on Circuits and Systems, Sevilla, Spain, 10/10/20. https://doi.org/10.1109/ISCAS45731.2020.9181183

TY - GEN

T1 - Implementation of a Nonlinear Self-Interference Canceller using High-Level Synthesis

AU - Lahti, Sakari

AU - Hämäläinen, Timo

AU - Pascual Campo, Pablo

AU - Anttila, Lauri

AU - Valkama, Mikko

AU - Lampu, Vesa

PY - 2020/10/21

Y1 - 2020/10/21

N2 - High-level synthesis (HLS) aims to improve the productivity of digital logic design over traditional register-transfer level (RTL) methods. This paper shows that HLS can replace RTL when implementing a complex data path oriented signal processing algorithm under strict throughput constraints. Our system is a nonlinear spline-based Hammerstein self-interference (SI) canceller for full-duplex transceiver capable of achieving high SI suppression, while maintaining low computational complexity. The achieved suppression of the SI is superb 45 dB, while consuming 29 026 of the available LUTs, 17992 of registers, and 655 of the DSP slices on Kintex-7 XC7K410T FPGA. Our paper also compares the usability of two commercial HLS tools that were used in this work.

AB - High-level synthesis (HLS) aims to improve the productivity of digital logic design over traditional register-transfer level (RTL) methods. This paper shows that HLS can replace RTL when implementing a complex data path oriented signal processing algorithm under strict throughput constraints. Our system is a nonlinear spline-based Hammerstein self-interference (SI) canceller for full-duplex transceiver capable of achieving high SI suppression, while maintaining low computational complexity. The achieved suppression of the SI is superb 45 dB, while consuming 29 026 of the available LUTs, 17992 of registers, and 655 of the DSP slices on Kintex-7 XC7K410T FPGA. Our paper also compares the usability of two commercial HLS tools that were used in this work.

KW - Field Programmable Gate Array (FPGA)

KW - Transceivers

KW - Radio frequency

KW - Full-duplex

KW - High-Level Synthesis

KW - Self-interference cancellation

U2 - 10.1109/ISCAS45731.2020.9181183

DO - 10.1109/ISCAS45731.2020.9181183

M3 - Conference contribution

SP - 1

EP - 5

BT - 2020 IEEE International Symposium on Circuits and Systems (ISCAS)

PB - IEEE

CY - Sevilla

T2 - IEEE International Symposium on Circuits and Systems

Y2 - 10 October 2020 through 21 October 2020

ER -

Implementation of a Nonlinear Self-Interference Canceller using High-Level Synthesis

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