Instruction Buffer with Limited Control Flow and Loop Nest Support

Vladimir Guzma, Teemu Pitkänen, Jarmo Takala

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    1 Citation (Scopus)
    89 Downloads (Pure)

    Abstract

    In this work, we present a minimalistic, energy efficient implementation of instruction buffer. We use loop detection and execution trace analysis to find most commonly executed loops in already scheduled application and tailor instruction buffer size to the size of most commonly executed loop(s). In addition to our previous work, we allow buffering of loops with limited control flow (early exit from the loop or early return to the beginning of the loop). We also show how analysis of loop nests can decrease the number of times loop body is copied from memory into the buffer. Our results show that in case of favorable loop nest, we can execute all but initial loop iterations from the instruction buffer, keeping instruction memory in the deselect mode.
    Translated title of the contributionInstruction Buffer with Limited Control Flow and Loop Nest Support
    Original languageEnglish
    Title of host publicationInternational Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-Samos, 2011, July 18-21, 2011, Samos, Greece
    Place of PublicationPiscataway, NJ
    PublisherIEEE
    Pages263-269
    ISBN (Print)978-1-4577-0802-2
    DOIs
    Publication statusPublished - 2011
    Publication typeA4 Article in a conference publication

    Publication series

    NameInternational Conference on Embedded Computer Systems: Architectures, Modeling and Simulation IC-Samos
    PublisherIEEE

    Publication forum classification

    • Publication forum level 1

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