Instruction Fetch Energy Reduction with Biased SRAMs

    Research output: Contribution to journalArticleScientificpeer-review

    12 Downloads (Pure)


    Especially in programmable processors, energy consumption of integrated memories can become a limiting design factor due to thermal dissipation power constraints and limited battery capacity. Consequently, contemporary improvement efforts on memory technologies are focusing more on the energy-efficiency aspects, which has resulted in biased CMOS SRAM cells that increase energy efficiency by favoring one logical value over another. In this paper, xor-masking, a method for exploiting such contemporary low power SRAM memories is proposed to improve the energy-efficiency of instruction fetching. Xor-masking utilizes static program analysis statistics to produce optimal encoding masks to reduce the occurrence of the more energy consuming instruction bit values in the fetched instructions. The method is evaluated on LatticeMico32, a small RISC core popular in ultra low power designs, and on a wide instruction word high performance low power DSP. Compared to the previous “bus invert” technique typically used with similar SRAMs, the proposed method reduces instruction read energy consumption of the LatticeMico32 by up to 13% and 38% on the DSP core.
    Original languageEnglish
    Pages (from-to)1519–1532
    Number of pages14
    JournalJournal of Signal Processing Systems
    Issue number11
    Publication statusPublished - Nov 2018
    Publication typeA1 Journal article-refereed

    Publication forum classification

    • Publication forum level 1


    Dive into the research topics of 'Instruction Fetch Energy Reduction with Biased SRAMs'. Together they form a unique fingerprint.

    Cite this