Macro Blocks in Synthesizable VHDL for Telecommunications ASICs

J. Jokela, P. Järvinen, J. Nurmi

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific

    Translated title of the contributionMacro Blocks in Synthesizable VHDL for Telecommunications ASICs
    Original languageEnglish
    Title of host publicationProc. NORCHIP'94 Gothenburg, Sweden, November 8-9, 1994
    Publication statusPublished - 1994
    Publication typeB3 Article in conference proceedings

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