Memory-Based FFT Architecture with Optimized Number of Multiplexers and Memory Usage

Zeynep Kaya, Mario Garrido, Jarmo Takala

Research output: Contribution to journalArticleScientificpeer-review


This brief presents a new P-parallel radix-2 memory-based fast Fourier transform (FFT) architecture. The aim of this work is to reduce the number of multiplexers and achieve an efficient memory usage. One advantage of the proposed architecture is that it only needs permutation circuits after the memories, which reduces the multiplexer usage to only one multiplexer per parallel branch. Another advantage is that the architecture calculates the same permutation based on the perfect shuffle at each iteration. Thus, the shuffling circuits do not need to be configured for different iterations. In fact, all the memories require the same read and write addresses, which simplifies the control even further and allows to merge the memories. Along with the hardware efficiency, conflict-free memory access is fulfilled by a circular counter. The FFT has been implemented on a field programmable gate array. Compared to previous approaches, the proposed architecture has the least number of multiplexers and achieves very low area usage.

Original languageEnglish
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Publication statusE-pub ahead of print - 2023
Publication typeA1 Journal article-refereed


  • Hardware
  • Indexes
  • Memory architecture
  • Memory management
  • Memory-based FFT
  • Multiplexing
  • perfect shuffle
  • radix-2
  • Signal processing algorithms
  • Writing

Publication forum classification

  • Publication forum level 2

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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