Memory Requirement Reduction of Deep Neural Networks for Field Programmable Gate Arrays Using Low-Bit Quantization of Parameters

Niccoló Nicodemo, Gaurav Naithani, Konstantinos Drossos, Tuomas Virtanen, Roberto Saletti

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

1 Citation (Scopus)

Abstract

Effective employment of deep neural networks (DNNs) in mobile devices and embedded systems, like field programmable gate arrays, is hampered by requirements for memory and computational power. In this paper we propose a method that employs a non-uniform fixed-point quantization and a virtual bit shift (VBS) to improve the accuracy of the quantization of the DNN weights. We evaluate our method in a speech enhancement application, where a fully connected DNN is used to predict the clean speech spectrum from the input noisy speech spectrum. A DNN is optimized, its memory requirement is calculated, and its performance is evaluated using the short-time objective intelligibility (STOI) metric. The application of the low-bit quantization leads to a 50% reduction of the DNN memory requirement while the STOI performance drops only by 2.7%.
Original languageEnglish
Title of host publication2020 28th European Signal Processing Conference (EUSIPCO)
PublisherIEEE
Pages466-470
Number of pages5
ISBN (Electronic)978-9-0827-9705-3
DOIs
Publication statusPublished - 2021
Publication typeA4 Article in a conference publication
EventEuropean Signal Processing Conference - Beurs van Berlage, Amsterdam, Netherlands
Duration: 18 Jan 202122 Jan 2021
Conference number: 28
https://eusipco2020.org

Publication series

NameEuropean Signal Processing Conference
ISSN (Electronic)2076-1465

Conference

ConferenceEuropean Signal Processing Conference
Abbreviated titleEUSIPCO2020
CountryNetherlands
CityAmsterdam
Period18/01/2122/01/21
Internet address

Keywords

  • Quantization (signal)
  • Neural networks
  • Memory management
  • Speech enhancement
  • Logic gates
  • Table lookup
  • Field programmable gate arrays
  • neural network quantization
  • memory footprint reduction
  • FPGA
  • hardware accelerators

Publication forum classification

  • Publication forum level 1

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