Modeling RISC-V processor in IP- XACT

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    1 Citation (Scopus)

    Abstract

    IP-XACT is the most used standard in IP (Intellectual Property) integration. It is intended as a language neutral golden reference, from which RTL and HW dependent SW is automatically generated. Despite its wide popularity in the industry, there are practically no public and open design examples for any part of the design flow from IP-XACT to synthesis. One reason is the difficulty of creating IP-XACT models for existing RTL projects. In this paper, we address the issues by modeling the PULPino RISC-V microprocessor that is written in SystemVerilog (SV) and the project distributed over several repositories. We propose how to solve the mismatching concepts between SV project and IP-XACT, and based on the findings propose improvements for the Kactus2 IP-XACT tool. In addition, the final PULPino model contributes to the rare public non-trivial examples for better adoption of the IP-XACT methodology.
    Original languageEnglish
    Title of host publicationProceedings - 21st Euromicro Conference on Digital System Design, DSD 2018
    PublisherIEEE
    Pages140-147
    ISBN (Electronic)9781538673768
    DOIs
    Publication statusPublished - 31 Aug 2018
    Publication typeA4 Article in a conference publication
    EventEuromicro Conference on Digital System Design - Prague, Czech Republic
    Duration: 29 Aug 201831 Aug 2018

    Conference

    ConferenceEuromicro Conference on Digital System Design
    Country/TerritoryCzech Republic
    CityPrague
    Period29/08/1831/08/18

    Publication forum classification

    • Publication forum level 1

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