TY - GEN
T1 - Models of architecture
T2 - IEEE International Workshop on Signal Processing Systems
AU - Pelcat, Maxime
AU - Desnos, Karol
AU - Maggiani, Luca
AU - Liu, Yanzhou
AU - Heulot, Julien
AU - Nezan, Jean François
AU - Bhattacharyya, Shuvra S.
PY - 2016/12/9
Y1 - 2016/12/9
N2 - The current trend in high performance and embedded signal processing consists of designing increasingly complex heterogeneous hardware architectures with non-uniform communication resources. In order to take hardware and software design decisions, early evaluations of the system non-functional properties are needed. These evaluations of system efficiency require high-level information on both the algorithms and the architecture. In this paper, we define the notion of Model of Architecture (MoA) and study the combination of a Model of Computation (MoC) and an MoA to provide a design space exploration environment for the study of the algorithmic and architectural choices. A cost is computed from the mapping of an application, represented by a model conforming a MoC onto an architecture represented by a model conforming an MoA. The cost is composed of a processing-related part and a communicationrelated part. It is an abstract scalar value to be minimized and can represent any non-functional requirement of a system such as memory, energy, throughput or latency.
AB - The current trend in high performance and embedded signal processing consists of designing increasingly complex heterogeneous hardware architectures with non-uniform communication resources. In order to take hardware and software design decisions, early evaluations of the system non-functional properties are needed. These evaluations of system efficiency require high-level information on both the algorithms and the architecture. In this paper, we define the notion of Model of Architecture (MoA) and study the combination of a Model of Computation (MoC) and an MoA to provide a design space exploration environment for the study of the algorithmic and architectural choices. A cost is computed from the mapping of an application, represented by a model conforming a MoC onto an architecture represented by a model conforming an MoA. The cost is composed of a processing-related part and a communicationrelated part. It is an abstract scalar value to be minimized and can represent any non-functional requirement of a system such as memory, energy, throughput or latency.
U2 - 10.1109/SiPS.2016.29
DO - 10.1109/SiPS.2016.29
M3 - Conference contribution
AN - SCOPUS:85013141986
T3 - IEEE International Workshop on Signal Processing Systems
SP - 121
EP - 126
BT - IEEE International Workshop on Signal Processing Systems, SiPS 2016
PB - IEEE
Y2 - 1 January 1900
ER -