Abstract
High-performance ray tracing on CPU is now largely based on Multi Bounding Volume Hierarchy (MBVH) trees. We apply MBVH to a fixed-function ray tracing accelerator architecture. According to cycle-level simulations and power analysis, MBVH reduces energy per frame by an average of 24% and improves performance per area by 19% in scenes with incoherent rays, due to its compact memory layout which reduces DRAM traffic. With primary rays, energy efficiency improves by 15% and performance per area by 20%.
| Original language | English |
|---|---|
| Title of host publication | SIGGRAPH ASIA 2016 Technical Briefs |
| Publisher | ACM |
| ISBN (Print) | 978-1-4503-4541-5 |
| DOIs | |
| Publication status | Published - 2016 |
| Publication type | A4 Article in conference proceedings |
| Event | ACM SIGGRAPH Asia - Duration: 1 Jan 1900 → … |
Conference
| Conference | ACM SIGGRAPH Asia |
|---|---|
| Period | 1/01/00 → … |
Keywords
- ray tracing, ray tracing hardware
Publication forum classification
- Publication forum level 1
Access to Document
- Camera ready manuscript
© ACM 2016. This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in Proceeding SA '16 SIGGRAPH ASIA 2016 Technical Briefs , http://dx.doi.org/10.1145/3005358.3005384