Multi-Level Parallelization Scheme for Distributed HEVC Encoding on Multi-Computer Systems

Sami Ahovainio; Alexandre Mercat; Marko Viitanen; Jarno Vanne

doi:10.1109/ISCAS45731.2020.9180975

Multi-Level Parallelization Scheme for Distributed HEVC Encoding on Multi-Computer Systems

Sami Ahovainio, Alexandre Mercat, Marko Viitanen, Jarno Vanne

Computing Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

2 Citations (Scopus)

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Abstract

High Efficiency Video Coding (HEVC) creates the conditions for cost-effective video transmission and storage but its inherent computational complexity calls for efficient parallelization techniques. This paper provides HEVC encoders with a holistic parallelization scheme that exploits parallelism at data, thread, and process levels at the same time. The proposed scheme is implemented in the practical Kvazaar open-source HEVC encoder. It makes Kvazaar exploit parallelism at three levels: 1) Single Instruction Multiple Data (SIMD) optimized coding tools at the data level; 2) Wavefront Parallel Processing (WPP) and Overlapped Wavefront (OWF) parallelization strategies at the thread level; and 3) distributed slice encoding on multi-computer systems at the process level. Our results show that the proposed process-level parallelization scheme increases the coding speed of Kvazaar by 1.86× on two computers and up to 3.92× on five computers with +0.19% and +0.81% coding losses, respectively. Exploiting all these three parallelism levels on a five-computer setup gives almost a 25× speedup over a non-parallelized single-core implementation.

Original language	English
Title of host publication	2020 IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher	IEEE
Number of pages	5
ISBN (Electronic)	978-1-7281-3320-1
ISBN (Print)	978-1-7281-3321-8
DOIs	https://doi.org/10.1109/ISCAS45731.2020.9180975
Publication status	Published - 2020
Publication type	A4 Article in conference proceedings
Event	IEEE International Symposium on Circuits and Systems - Sevilla, Spain Duration: 10 Oct 2020 → 21 Oct 2020 https://iscas2020.org/

Publication series

Name	IEEE International Symposium on Circuits and Systems proceedings
ISSN (Print)	0271-4302
ISSN (Electronic)	2158-1525

Conference

Conference	IEEE International Symposium on Circuits and Systems
Abbreviated title	ISCAS 2020
Country/Territory	Spain
City	Sevilla
Period	10/10/20 → 21/10/20
Internet address	https://iscas2020.org/

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Publication forum level 1

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title = "Multi-Level Parallelization Scheme for Distributed HEVC Encoding on Multi-Computer Systems",

abstract = "High Efficiency Video Coding (HEVC) creates the conditions for cost-effective video transmission and storage but its inherent computational complexity calls for efficient parallelization techniques. This paper provides HEVC encoders with a holistic parallelization scheme that exploits parallelism at data, thread, and process levels at the same time. The proposed scheme is implemented in the practical Kvazaar open-source HEVC encoder. It makes Kvazaar exploit parallelism at three levels: 1) Single Instruction Multiple Data (SIMD) optimized coding tools at the data level; 2) Wavefront Parallel Processing (WPP) and Overlapped Wavefront (OWF) parallelization strategies at the thread level; and 3) distributed slice encoding on multi-computer systems at the process level. Our results show that the proposed process-level parallelization scheme increases the coding speed of Kvazaar by 1.86× on two computers and up to 3.92× on five computers with +0.19% and +0.81% coding losses, respectively. Exploiting all these three parallelism levels on a five-computer setup gives almost a 25× speedup over a non-parallelized single-core implementation. ",

author = "Sami Ahovainio and Alexandre Mercat and Marko Viitanen and Jarno Vanne",

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language = "English",

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Ahovainio, S, Mercat, A , Viitanen, M & Vanne, J 2020, Multi-Level Parallelization Scheme for Distributed HEVC Encoding on Multi-Computer Systems. in 2020 IEEE International Symposium on Circuits and Systems (ISCAS)., 9180975, IEEE International Symposium on Circuits and Systems proceedings, IEEE, IEEE International Symposium on Circuits and Systems, Sevilla, Spain, 10/10/20. https://doi.org/10.1109/ISCAS45731.2020.9180975

Multi-Level Parallelization Scheme for Distributed HEVC Encoding on Multi-Computer Systems. / Ahovainio, Sami; Mercat, Alexandre ; Viitanen, Marko et al.
2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2020. 9180975 (IEEE International Symposium on Circuits and Systems proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

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T1 - Multi-Level Parallelization Scheme for Distributed HEVC Encoding on Multi-Computer Systems

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AU - Viitanen, Marko

AU - Vanne, Jarno

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PY - 2020

Y1 - 2020

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AB - High Efficiency Video Coding (HEVC) creates the conditions for cost-effective video transmission and storage but its inherent computational complexity calls for efficient parallelization techniques. This paper provides HEVC encoders with a holistic parallelization scheme that exploits parallelism at data, thread, and process levels at the same time. The proposed scheme is implemented in the practical Kvazaar open-source HEVC encoder. It makes Kvazaar exploit parallelism at three levels: 1) Single Instruction Multiple Data (SIMD) optimized coding tools at the data level; 2) Wavefront Parallel Processing (WPP) and Overlapped Wavefront (OWF) parallelization strategies at the thread level; and 3) distributed slice encoding on multi-computer systems at the process level. Our results show that the proposed process-level parallelization scheme increases the coding speed of Kvazaar by 1.86× on two computers and up to 3.92× on five computers with +0.19% and +0.81% coding losses, respectively. Exploiting all these three parallelism levels on a five-computer setup gives almost a 25× speedup over a non-parallelized single-core implementation.

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ER -

Multi-Level Parallelization Scheme for Distributed HEVC Encoding on Multi-Computer Systems

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