Multiplier-Free Decimators with Efficient VLSI Implementation for Sigma-Delta A/D Converters

H. Palomäki, T. Saramäki, H. Tenhunen

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    Translated title of the contributionMultiplier-Free Decimators with Efficient VLSI Implementation for Sigma-Delta A/D Converters
    Original languageEnglish
    Title of host publicationPresented in IEEE Workshop on VLSI Signal Processing (Monterey, CA), Nov. 1988; included in VLSI Signal Processing 3, edited by R.W. Brodersen and H.S.Moscovitz
    Place of PublicationNew York
    PublisherIEEE Press
    Pages523-534
    Publication statusPublished - 1988
    Publication typeA4 Article in conference proceedings

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