TY - GEN
T1 - Multiprocessor scheduling of dataflow programs within the reconfigurable video coding framework
AU - Boutellier, Jani
AU - Lucarz, Christophe
AU - Gomez, Victor Martin
AU - Mattavelli, Marco
AU - Silvén, Olli
PY - 2011
Y1 - 2011
N2 - The new Reconfigurable Video Coding (RVC) standard of MPEG marks a transition in the way video coding algorithms are specified. Imperative and monolithic reference software is replaced by a collection of interconnected, concurrent functional units (FUs) that are specified with the actor-oriented CAL language. Different connections between the FUs lead to different decoders: all previous standards (MPEG-2 MP, MPEG-4 SP, AVC, SVC, ⋯) can be built with RVC FUs. The RVC standard does not specify a schedule or scheduling heuristic for running the decoder implementations consisting of FUs. Previous work has shown a way to produce efficient quasi-static schedules for CAL actor networks. This paper discusses the mapping of RVC FUs to multiprocessor systems, utilizing quasi-static scheduling. A design space exploration tool has been developed, that maps the FUs to a multiprocessor system in order to maximize the decoder throughput. Depending on the inter-processor communication cost, the tool points out different mappings of FUs to processing elements.
AB - The new Reconfigurable Video Coding (RVC) standard of MPEG marks a transition in the way video coding algorithms are specified. Imperative and monolithic reference software is replaced by a collection of interconnected, concurrent functional units (FUs) that are specified with the actor-oriented CAL language. Different connections between the FUs lead to different decoders: all previous standards (MPEG-2 MP, MPEG-4 SP, AVC, SVC, ⋯) can be built with RVC FUs. The RVC standard does not specify a schedule or scheduling heuristic for running the decoder implementations consisting of FUs. Previous work has shown a way to produce efficient quasi-static schedules for CAL actor networks. This paper discusses the mapping of RVC FUs to multiprocessor systems, utilizing quasi-static scheduling. A design space exploration tool has been developed, that maps the FUs to a multiprocessor system in order to maximize the decoder throughput. Depending on the inter-processor communication cost, the tool points out different mappings of FUs to processing elements.
UR - http://www.scopus.com/inward/record.url?scp=78651524323&partnerID=8YFLogxK
U2 - 10.1007/978-90-481-9965-5_11
DO - 10.1007/978-90-481-9965-5_11
M3 - Conference contribution
AN - SCOPUS:78651524323
SN - 9789048199648
VL - 73 LNEE
T3 - Lecture Notes in Electrical Engineering
SP - 237
EP - 251
BT - Algorithm-Architecture Matching for Signal and Image Processing - Best Papers from Design and Architectures for Signal and Image Processing 2007 and 2008 and 2009
ER -