On-line reconfigurable extended generalized fat tree network-on-chip for multiprocessor system-on-chip circuits

H. Kariniemi

    Research output: Book/ReportDoctoral thesisCollection of Articles

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    The System-on-Chip (SoC) circuits contain already today a large number of processors and other blocks, which sets several hard requirements to their communication infrastructures implemented with Networks-On-Chip (NOC). The NOCs are a generally accepted concept in the semiconductor industry for solving the problems related with an on-chip communication which include among other things high wire delays and increasing clock skew. Other problems related to on-chip communication are the scalability of the NOC topologies for different systems sizes and for different performance and reliability requirements. This thesis concerns the implementation of communication infrastructures with eXtended Generalized Fat Tree (XGFT) Network-On-Chip (NOC) for Multi-Processor SoCs (MPSoC). Actually this thesis presents two different NOCs, because the XGFT NOC is compared with a two-dimensional (2-D) mesh NOC which was especially developed and designed for this purpose. The 2-D mesh is used as a reference NOC, because it is the most commonly used topology in different NOC implementations presented by today. An important issue in the NOC design is routing, and therefore, both adaptive and deterministic routing in the XGFTs is concerned quite thoroughly in this thesis. The performances of different XGFTs are also evaluated and compared in order to explain how the routing affects the performance and how the scalability of the XGFT topology could be exploited in optimizing the NOCs. One of the important issues also concerned in this thesis is the Quality-of-Service (QoS) which simple NOCs are able to provide. Usually Time-Division-Multiplexing (TDM) and accurate allocation of communication resources is required for implementing guaranteed QoS. However, the QoS can also be improved by other simpler methods presented in this thesis, although these methods can not provide guaranteed QoS of any kind. Owing to the increasing number of transistors, wires, and intellectual property blocks the testing of the SoCs is becoming more complex. The future deep sub-micron (DSM) VLSI technologies are also more complex technologies which increases the defect densities in addition to the previously mentioned facts. As a consequence of this, a special attention must be paid for making the NOCs as reliable as possible and for improving their manufacturability. This can be achieved by exploiting the redundant resources of the NOCs and by using different mechanisms for reconfiguring the faulty NOCs so that they could operate correctly despite the defects. This thesis shows how this can be done with a new Fault-Diagnosis-And-Repair (FDAR) system which is used together with a fault-tolerant routing in both the XGFT NOCs and the 2-D mesh NOCs. The FDAR system improves also the manufacturability of the SoCs, since it can be used for reconfiguring the faulty NOCs on-line to work properly as the title of this thesis also suggests. Because defect densities are increasing and the testing of the SoCs is becoming more complex, systems like the FDAR which allow on-line self-diagnosis and self-repair will become necessary. This is also possible owing to the large number of redundant hardware resources which the MPSoCs have for both computing and communication.
    Translated title of the contributionOn-line reconfigurable extended generalized fat tree network-on-chip for multiprocessor system-on-chip circuits
    Original languageEnglish
    Place of PublicationTampere
    PublisherTampere University of Technology
    Number of pages144
    ISBN (Electronic)952-15-1746-8
    ISBN (Print)952-15-1651-8
    Publication statusPublished - 27 Sep 2006
    Publication typeG5 Doctoral dissertation (article)

    Publication series

    NameTampere University of Technology. Publication
    PublisherTampere University of Technology
    ISSN (Print)1459-2045

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