Parallel processing intensive digital front-end for IEEE 802.11ac receiver

Mona Aghababaeetafreshi, Juha Yli-Kaakinen, Toni Levanen, Ville Korhonen, Pekka Jääskeläinen, Markku Renfors, Mikko Valkama, Jarmo Takala

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    1 Citation (Scopus)
    12 Downloads (Pure)


    Modern computing platforms offer increasing levels of parallelism for fast execution of different signal processing tasks. In this paper, we develop and elaborate on a digital front-end concept for an IEEE 802.11ac receiver with 80 MHz bandwidth where parallel processing is adopted in multiple ways. First, the inherent structure of the 802.11ac waveform is utilized such that it is divided, through time-domain digital filtering and decimation, to two parallel 40 MHz signals that can be processed further in parallel using smaller-size FFTs and, e.g, legacy 802.11n digital receiver chains. This filtering task is very challenging, as the latency and the cyclic prefix budget of the receiver cannot be compromised, and because the number of unused subcarriers in the middle of the 80 MHz signal is only three, thus necessitating very narrow transition bandwidth in the deployed filters. Both linear and circular filtering based multirate channelization architectures are developed and reported, together with the corresponding filter coefficient optimization. Also, full radio link performance simulations with commonly adopted indoor WiFi channel profiles are provided, verifying that the channelization does not degrade the overall link performance. Then, both C and OpenCL software implementations of the processing are developed and simulated for comparison purposes on an Intel CPU, to demonstrate that the parallelism provided by the OpenCL will result in substantially faster realization. Furthermore, we provide complete software implementation results in terms of time, number of clock cycles, power, and energy consumption on the ARM Mali GPU with half precision floating-point arithmetic along with the ARM Cortex A7 CPU.
    Original languageEnglish
    Title of host publication2015 49th Asilomar Conference on Signals, Systems and Computers
    Number of pages8
    ISBN (Electronic)978-1-4673-8576-3
    ISBN (Print)978-1-4673-8574-9
    Publication statusPublished - 2016
    Publication typeA4 Article in conference proceedings
    EventAsilomar Conference on Signals, Systems & Computers - California, Pacific Grove, United States
    Duration: 8 Nov 201511 Nov 2015

    Publication series

    ISSN (Electronic)1058-6393


    ConferenceAsilomar Conference on Signals, Systems & Computers
    Country/TerritoryUnited States
    CityPacific Grove

    Publication forum classification

    • Publication forum level 1


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