Power Optimizations for Transport Triggered SIMD Processors

Joonas Multanen; Timo Viitanen; Henry Linjamäki; Heikki Kultala; Pekka Jääskeläinen; Jarmo Takala; Lauri Koskela; Jesse Simonsson; Heikki Berg; Kalle Raiskila; Tommi Zetterman

doi:10.1109/SAMOS.2015.7363689

Power Optimizations for Transport Triggered SIMD Processors

Joonas Multanen, Timo Viitanen, Henry Linjamäki, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Lauri Koskela, Jesse Simonsson, Heikki Berg, Kalle Raiskila, Tommi Zetterman

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

2 Citations (Scopus)

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Abstract

Power consumption in modern processor design is a key aspect. Optimizing the processor for power leads to direct savings in battery energy consumption in case of mobile devices. At the same time, many mobile applications demand high computational performance. In case of large scale computing, low power compute devices help in thermal design and in reducing the electricity bill. This paper presents a case study of a customized low power vector processor design that was synthesized on a 28 nm process technology. The processor has a programmer exposed datapath based on the transport triggered architecture programming model. The paper’s focus is on the RTL and microarchitecture level power optimizations applied to the design. Using register file datapath gating, register file banking and enabling clock gating of individual pipeline stages in pipelined function units, up to one fourth of power and energy savings could be achieved with only a small area overhead. On top of this, for the measured radio applications, the exposed datapath architecture helped to achieve major power improvements in comparison to the traditional VLIW programming model by utilizing optimizations unique to transport triggered architectures.

Original language	English
Title of host publication	2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XV, Agios Konstantinos, Samos, Greece
Publisher	IEEE
Pages	303-309
Number of pages	7
ISBN (Print)	978-1-4673-7311-1
DOIs	https://doi.org/10.1109/SAMOS.2015.7363689
Publication status	Published - 2015
Publication type	A4 Article in conference proceedings
Event	International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation - Duration: 1 Jan 1900 → …

Conference

Conference	International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
Period	1/01/00 → …

Keywords

low-power
transport triggered architecture

Publication forum classification

Publication forum level 1

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/SAMOS.2015.7363689

PowerOptimizationsforTTASIMDProcessors
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Accepted author manuscript, 332 KB

http://urn.fi/URN:NBN:fi:tty-201702061096

Cite this

Multanen, J., Viitanen, T., Linjamäki, H., Kultala, H., Jääskeläinen, P., Takala, J., Koskela, L., Simonsson, J., Berg, H., Raiskila, K., & Zetterman, T. (2015). Power Optimizations for Transport Triggered SIMD Processors. In 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XV, Agios Konstantinos, Samos, Greece (pp. 303-309). IEEE. https://doi.org/10.1109/SAMOS.2015.7363689

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abstract = "Power consumption in modern processor design is a key aspect. Optimizing the processor for power leads to direct savings in battery energy consumption in case of mobile devices. At the same time, many mobile applications demand high computational performance. In case of large scale computing, low power compute devices help in thermal design and in reducing the electricity bill. This paper presents a case study of a customized low power vector processor design that was synthesized on a 28 nm process technology. The processor has a programmer exposed datapath based on the transport triggered architecture programming model. The paper{\textquoteright}s focus is on the RTL and microarchitecture level power optimizations applied to the design. Using register file datapath gating, register file banking and enabling clock gating of individual pipeline stages in pipelined function units, up to one fourth of power and energy savings could be achieved with only a small area overhead. On top of this, for the measured radio applications, the exposed datapath architecture helped to achieve major power improvements in comparison to the traditional VLIW programming model by utilizing optimizations unique to transport triggered architectures. ",

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Multanen, J, Viitanen, T, Linjamäki, H, Kultala, H, Jääskeläinen, P , Takala, J, Koskela, L, Simonsson, J, Berg, H, Raiskila, K & Zetterman, T 2015, Power Optimizations for Transport Triggered SIMD Processors. in 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XV, Agios Konstantinos, Samos, Greece. IEEE, pp. 303-309, International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, 1/01/00. https://doi.org/10.1109/SAMOS.2015.7363689

Power Optimizations for Transport Triggered SIMD Processors. / Multanen, Joonas; Viitanen, Timo; Linjamäki, Henry et al.
2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XV, Agios Konstantinos, Samos, Greece. IEEE, 2015. p. 303-309.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Power Optimizations for Transport Triggered SIMD Processors

AU - Multanen, Joonas

AU - Viitanen, Timo

AU - Linjamäki, Henry

AU - Kultala, Heikki

AU - Jääskeläinen, Pekka

AU - Takala, Jarmo

AU - Koskela, Lauri

AU - Simonsson, Jesse

AU - Berg, Heikki

AU - Raiskila, Kalle

AU - Zetterman, Tommi

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N2 - Power consumption in modern processor design is a key aspect. Optimizing the processor for power leads to direct savings in battery energy consumption in case of mobile devices. At the same time, many mobile applications demand high computational performance. In case of large scale computing, low power compute devices help in thermal design and in reducing the electricity bill. This paper presents a case study of a customized low power vector processor design that was synthesized on a 28 nm process technology. The processor has a programmer exposed datapath based on the transport triggered architecture programming model. The paper’s focus is on the RTL and microarchitecture level power optimizations applied to the design. Using register file datapath gating, register file banking and enabling clock gating of individual pipeline stages in pipelined function units, up to one fourth of power and energy savings could be achieved with only a small area overhead. On top of this, for the measured radio applications, the exposed datapath architecture helped to achieve major power improvements in comparison to the traditional VLIW programming model by utilizing optimizations unique to transport triggered architectures.

AB - Power consumption in modern processor design is a key aspect. Optimizing the processor for power leads to direct savings in battery energy consumption in case of mobile devices. At the same time, many mobile applications demand high computational performance. In case of large scale computing, low power compute devices help in thermal design and in reducing the electricity bill. This paper presents a case study of a customized low power vector processor design that was synthesized on a 28 nm process technology. The processor has a programmer exposed datapath based on the transport triggered architecture programming model. The paper’s focus is on the RTL and microarchitecture level power optimizations applied to the design. Using register file datapath gating, register file banking and enabling clock gating of individual pipeline stages in pipelined function units, up to one fourth of power and energy savings could be achieved with only a small area overhead. On top of this, for the measured radio applications, the exposed datapath architecture helped to achieve major power improvements in comparison to the traditional VLIW programming model by utilizing optimizations unique to transport triggered architectures.

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KW - transport triggered architecture

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DO - 10.1109/SAMOS.2015.7363689

M3 - Conference contribution

SN - 978-1-4673-7311-1

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EP - 309

BT - 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XV, Agios Konstantinos, Samos, Greece

PB - IEEE

T2 - International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

Y2 - 1 January 1900

ER -

Power Optimizations for Transport Triggered SIMD Processors

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Keywords

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